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242 CHAPTER 6 / NONARITHMETIC COMBINATIONAL LOGIC DEVICES

assist the reader in developing good design practices, the following six-step sequence is
recommended:
Step 1: Understand the device. Describe the function of the device; then clearly
indicate its input/output (I/O) specifications and timing constraints, and con-
struct its block diagram(s).
Step 2: State any relevant algorithms. State all algorithms and/or binary ma-
nipulations necessary for the design. Include a general operations format if
necessary.
Step 3: Construct the truth tables. From step 2, construct the truth tables that
detail the I/O relationships. Truth tables are usually presented in positive logic
form.
Step 4: Obtain the output functions. Map or use a minimization program to
obtain any minimum or reduced expressions that may be required for the output
functions.
Step 5: Construct the logic diagrams. Use either a gate or modular level ap-
proach (or both) to implement the logic expressions obtained in step 4. Imple-
ment from output to input, taking into account any mixed logic I/O conditions
and timing constraints that may be required.
Step 6: Check the results. Check the final logic circuit by simulation before
implementation as a physical device. Real-time tests of the physical device
should be the final test stage.

This text follows the six-step sequence where appropriate and does so without specifically
mentioning each step.

6.2 MULTIPLEXERS

There is a type of device that performs the function of selecting one of many data input
lines for transmission to some destination. This device is called a multiplexer (MUX for
short) or data selector. It requires n data select lines to control 2" data input lines. Thus,
a MUX is a 2" -input/ 1 -output device (excluding the n data select inputs) identified by the
block diagram in Fig. 6.3a. Shown in Fig. 6.3b is the mechanical switch equivalent of the
MUX. Notice that the function of the enable (EN = G) is to provide a disable capability to
the device. Commercial MUX ICs usually come with active low enable, EN(L).
The general logic equation for the MUX of Fig. 6.3 can be expressed as
2"-l
Y = (m,- • /,) - EN, (6.4)

where w/ represents the ith minterm of the data select inputs (e.g., m^ — S n-\ •
The validity of this equation will be verified in the following subsection on multiplexer
design.

6.2.1 Multiplexer Design
The easiest and most "logical" way to design a MUX is to represent the MUX by a com-
pressed, entered variable (EV) truth table. This is illustrated by the design of a 4-to-l