Page 360 - Engineering Digital Design

PROBLEMS 331

[17] The Programmable Logic Data Book. Xilinx, Inc., San Jose, CA, 1996.
[18] XACT, Logic Cell Array Macro Library. Xilinx, Inc., San Jose, CA, 1992.

PROBLEMS

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7.1 A 2 x 4 ROM is to be used to implement the following system of three functions,
assuming that all inputs and outputs are active high.

yi(a,b,c,d) = ^m(Q, 1,2,5,7,8, 10, 14, 15)
y 2(a, b, c,d) = Y^ m(Q, 2, 4, 5, 6, 7, 8, 10, 12)

y 3(a,b, c,</) = Vm(0, 1,2,3,4,6,8,9, 10, 11)

(a) Construct the ROM program table for this system of three functions.
(b) From the program table of part (a), construct the symbolic representation of fusible
links by following the example in Fig. 7.4.
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7.2 A 2 x 4 ROM is to be used to design and implement a BCD-to-binary module that
can be cascaded to produce any size of a BCD-to-binary converter (e.g., see Fig. 6.21).
(a) Construct the ROM program table for this module following Fig. 6.20.
(b) From the program table in part (a), construct a symbolic representation of the
fusible links by referring to the example in Fig. 7.4.
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7.3 A 2 x 4 PROM is to be used to implement the following system of three functions:

Fi(A,B,C) = Y[M(Q, 2,4)
F 2(A, B, C, D) = l~f Af(3-12)

i, 3,5,7)

(a) Construct the program table for this ROM if the inputs arrive as A(//), B(H),
C(L), and D(H), and the outputs are FI(#), F 2(L), and F 3(//). Use of inverters
is not permitted.
(b) From the program table in part (a), construct a symbolic representation of the
fusible links following the example in Fig. 7.4.
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7.4 A multiplexed scheme of 2 x 4 EPROMs is to be used to design and implement a
circuit that will convert 8-bit one-hot code (see Table 2.11) to 4-bit binary. Assume
that all false data are rejected and indicated by binary 1000.
(a) In place of a ROM program table, give the coded canonical SOP forms for each
binary output.
(b) Illustrate with a block diagram how the outputs of the multiplexed scheme must
be wired-ORed to produce the four binary outputs of the converter. (Refer to
Section 7.6 and Figs. 7.14 and 7.15 for a discussion of multiplexed schemes and
wired-ORed connections.)