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328 CHAPTER 7 / PROGRAMMABLE LOGIC DEVICES

longlines only via tri-state drivers. Programmable interconnect points between longlines
and single-length lines are available. However, no interconnect points are provided between
double-length lines and others.
Logic cell arrays (LCAs), such as the XC4000 series FPGAs, have the unique property
that they can be reconfigured within a system and can even be dynamically altered to perform
different functions at different times in a process. This family of devices contain 16x1 and
32x1 static RAM primitives that are user-configurable via look-up tables. Self-diagnosis,
hardware for different environments, or dual-purpose applications — these exemplify the
versatility that is inherent in reconfigurable LCAs. Properly used, such devices can minimize
design effort and reduce costs. However, all of the above are possible only with the use of
CAD help, the topic of Section 7.8. For much more complete information on Xilinx FPGAs,
the reader is referred to Further Reading at the end of this chapter.

7.7.4 Other Classes of General-Purpose PLDs

To provide the reader with an overall perspective on the diversity of general-purpose PLDs
and for reference purposes, the following additional classes of complex PLDs (CPLDs) are
offered as an extension of the devices discussed in the previous two subsections:

Generic Array Logic (GAL) Devices: Erasable MSI PLDs that may contain
AOIs, XOR gates, and registers in the output stage for sequential machine
design. GAL is a registered trademark of Lattice Semiconductor, Hillsboro,
OR 97124.
Erasable programmable logic devices (EPLDs): Erasable CMOS-based de-
vices whose macrocells typically contain discrete gates, MUXs, and registers
(flip-flops) for sequential machine design. Some EPLDs may contain arithmetic
logic units (ALUs). Both Altera and Xilinx Corporation offer EPLDs of vari-
ous complexity. Detailed information on EPLDs are available from the Altera
Data Book, Altera Corporation, and from The Programmable Logic Data Book,
Xilinx Corporation, 1994.
Field programmable logic sequencers (FPLS): Similar to PAL and GAL de-
vices that have output logic consisting of discrete gates and flip-flops. Detailed
information on these devices is available from Phillips, Programmable Logic
Devices (PLD) Handbook, Phillips Semiconductor, Sunnyvale, CA, 1994; and
Programmable Logic Data Handbook, Signetics Co., Sunnyvale, CA, 1992.

7.8 CAD HELP IN PROGRAMMING PLD DEVICES

The programming of a PAL 1C device, like that of a ROM or PLA, can be accomplished by
a physical device (a programmer) that applies voltage pulses to target fusible links, causing
disconnection of the bit positions as discussed in Section 7.2. The programmer may be a
dedicated device or one of universal capability for ROMs, PLAs, and PAL devices, and it
may even have erasure capability. In any case, the difficult part of the programming process
is providing the instructions required to fit the Boolean expressions into the capability of
the specific PLD device, for example, a PAL device, that may support an L-, R-, or V-type