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7.8 CAD HELP IN PROGRAMMING PLD DEVICES 329

macrocell structure. This difficulty is overcome by proprietary software from manufacturers
of PLD devices and PLD device programmers. A commonly used CAD package for this
purpose is called ABEL (for Advanced Boolean Expression Language, a product of DATA
I/O Corp., Redmond, WA). The ABEL compiler accepts I/O data in tabular form, minimizes
it by using algorithms based on Espresso (discussed in Section 4.8), and generates a fuse
map that can be read in one of several standard formats by the programming device: JEDEC
(Joint Electron Device Engineering Council) format, ASCII hex format, Intel Hex format,
etc. As the name implies, the fuse map (pattern) targets those fusible links that must be
disconnected.
ABEL is not the only PLD programming compiler that is currently in use for PAL devices.
A CAD software called PALASM (for PAL assembler) is commonly used to convert SOP
Boolean expressions or truth tables into fuse maps for PAL devices. I/O pin specifications on
the chip are required. Like ABEL, the PALASM compiler generates a fuse map in JEDEC
format that can be read by the PAL programming device. PALASM is available without
cost from AMD Inc. (Advanced Micro Devices, Inc.).
For Xilinx FPGA devices, dedicated and sophisticated CAE (computer-aided engineer-
ing) software called XACT (for Xilinx automated CAE tools) is available from the Xilinx
Corp. XACT uses a three-step interrelated and iterative design process: design entry, design
implementation, and design verification. For design entry at the gate level, the designer
may begin with a schematic capture and labeling of the circuit to be implemented. To do
this the designer can choose Viewlogic's Viewdraw, Mentor Graphics' Design Architect, or
OrCAD's SDT, since these are all supported by the XACT development system. Design en-
try at the behavioral level (for example, Boolean equations or state machine descriptions) is
best accomplished by the Xilinx-ABEL and X-BLOX products of Xilinx and other products
by CAE vendors. Also, for complex systems, the use of high-level hardware description
languages such as VHDL is recommended. Xilinx offers HDL interfaces for synthesis tools
from synopsis and Viewlogic Systems. Mentor Graphics, Cadence Design Systems, and
Exemplar Logic also offer HDL synthesis tools fashioned for Xilinx FPGAs.
One advantage of the Xilinx design environment is that the designers can combine
schematic, text, gate-level, and behavioral-level descriptions at the design entry stage and
then reuse such descriptions within the same system or in other systems at some future time.
This is called mix-mode design entry and can be carried out by using different design entry
tools, allowing the designer to choose the most effective and efficient design tool for each
portion of the design.
Following the design entry comes the design implementation. Here, the FPGA design
entry tools are mapped into the resources of the target device architecture, optimally select-
ing the routing channels that connect the CLBs and lOBs of the logic cell array. Although
this can be accomplished automatically, the designer can and should exert control over the
implementation process to minimize potential problems. For this purpose the Xilinx design
environment provides an interactive, graphics-based editor that permits user manipulation
of the logic and routing schemes for the FPGA device.
The design verification is the last part of the design process and necessarily follows
the implementation stage. In-circuit testing, simulation at various levels, and static timing
analysis are involved in the verification stage. This is accomplished by use of timing cal-
culators, back-annotation capability, and static timing analyzers, which are available from
Xilinx Corp. and various third-party vendors.