Page 362 - Engineering Digital Design

PROBLEMS 333

examples, implement each of the following logic functions by using a single ACT-1
module assuming all inputs are active high: [Hint: Use Fig. 7.24, not Eq. (7.5), and
plan to include O's and 1's as inputs where needed.]
(a) Y(H) = (A + B)(H) = A • B(L) A two-input NAND gate
(b) Y(H) = ABC(H} = (A + B + C)(L) A p-term (or s-term)
(c) Y(H) = (AB + A £)(//) = [(A + E)(A + B)](L) Defining relations for XOR
(d) Y(A, B, C)(H) = Sm(2, 3, 5, 7)(tf) Canonical SOP function
7.11 The AOI and OAI gates in Figs. 7.21, 7.22, and 7.23 are versatile building blocks that
can be used in the implementation of a variety of logic functions. Simple examples
are given in Subsection 7.7.1. With a minimum of external logic, apply these AOI and
OAI gates in creative ways to implement the following functions:
(a) Use one AOI gate (nothing else) to implement the expression for (A = B)(H)
given by Eq. (6.22).
(b) Use a minimum number of AOI gates to implement the three-function system in
Problem 7.6 with input and output activation levels as stated. (Hint: For F\, use
Fig. 7.23)
(c) Use a minimum number of OAI gates to implement the three-function system in
Problem 7.3 with input and output activation levels as stated. (Hint: For F 2, use
the dual of Fig. 7.23.)