Page 361 - Engineering Digital Design

332 CHAPTER 7 / PROGRAMMABLE LOGIC DEVICES

7.5 Design an XS3-to-Gray code converter by using a 4 x 8 x 4 FPLA. Assume that all
inputs and outputs are active high and that false data are not rejected.
(a) Construct the minimized p-term table for this converter.
(b) From the p-term table in part (a), construct the symbolic representation for the
fusible links following the example in Fig. 7.10.

7.6 The following three functions are to be implemented by using a 4 x 8 x 4 FPLA.

FI = AB + ABC + BC + AC
F 2 = A® (BC}

(a) Construct the minimized p-term table for the three functions. Assume that the in-
puts arrive as A(H), B(H\ and C(L) and that the outputs are issued as FI (//), F 2(L),
and F 3(H).
(b) From the p-term table in part (a), construct the symbolic representation for the
fusible links following the example in Fig. 7.10. An inverter is permitted on the
active low input.
7.7 A BCD-to-XS3 code converter is to be designed by using a 4 x 12x4 PAL.
(a) Construct the minimized p-term table for this converter. Assume that the inputs
and outputs are all active low, and that all false data are encoded as 0000. Keep in
mind that PALs cannot take advantage of shared Pis as can PLAs.
(b) From the p-term table of part (a), construct the symbolic representation for the
fusible links following the example in Fig. 7.11. Inverters may be used on the
inputs.
7.8 A cascadable 2-bit comparator is to be designed by using a PAL.
(a) Given the compressed truth table and EV K-maps in Fig. 6.28, find the minimum
SOP logic expressions for the three outputs and construct the minimum p-term
table from these expressions. Assume that all inputs and outputs are active high.
(b) From the p-term table in part (a), determine the minimum size PAL that can be
used and then construct the symbolic representation of the fusible links for this
comparator. Include tri-state enables.
7.9 The three functions in Problem 7.1 are to be designed by using a 4 x 16x4 PAL.
(a) Construct the minimized p-term table for these three functions keeping in mind
that a PAL cannot take advantage of shared Pis as can PLAs. Assume that the
inputs arrive as a(L), b(L), c(H), and d(H), and that the outputs must be issued
as y\ (H), j2(L\ and yi(H}. Note that inverters are not permitted on the inputs.
(b) From the program table of part (a), construct the symbolic representation of fusible
links by following a form similar to that of Fig. 7.1 1, but with tri-state enables on
the outputs.
7.10 The Actel (ACT-1) logic module, shown in Fig. 7.24, is embedded by the hundreds
in Actel's FPGAs. This module is remarkably versatile in its ability to implement a
large number of simple SOP functions active high, or POS functions active low. As