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CHAPTER 9

Propagation Delay and Timing

Defects in Combinational Logic

9.1 INTRODUCTION

To this point in the text, combinational logic circuits have been treated as though they
were composed of "ideal" gates in the sense of having no propagation delay. Now it is
necessary to take a step into the real world and consider that each gate has associated
with it a propagation time delay and that, as a result of this delay, undesirable effects may
occur.
Under certain conditions unwanted transients can occur in otherwise steady-state signals.
These transients have become known as glitches, a term that derives from the German
glitsche, meaning a "slip" (hence, the slang, error or mishap). A glitch is a type of logic
noise that is undesirable because its presence in an output may initiate an unwanted process
in a next-stage switching device to which that output is an input. In some circuits glitches
can be avoided through good design practices; in other circuits they are unavoidable and
must be dealt with accordingly.
There are three kinds of logic noise that occur in combinational logic circuits and that
are classified as hazards.

Static hazards:
Static 1-hazard (also called SOP hazard) — A glitch that occurs in an otherwise
steady-state 1 output signal from SOP logic because of a change in an input
for which there are two asymmetric paths (delay-wise) to the output.
Static 0-hazard (also called POS hazard) — A glitch that occurs in an otherwise
steady-state 0 output signal from POS logic because of a change in an input
for which there are two asymmetric paths (delay-wise) to the output.

Static 1-Hazard Static 0-Hazard

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