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11.3 DETECTION AND ELIMINATION OF STATIC HAZARDS 499

D flip-flop. Notice that one-half of a clock cycle is lost because of the action of the filter. If
the D flip-flop is triggered in phase with the FSM memory flip-flops, an entire clock cycle
will be lost in the filtering process. To help understand how the filtering process eliminates
logic noise such as ORGs, the following is presented for reference purposes:

Remember: All forms of logic noise (glitches), including ORGs, occur immediately
following the triggering edge of the clock waveform, and the duration of any logic
noise pulse will always be much less than one-half the clock period.

Because logic noise occurs immediately following the triggering edge (RET or FET) of
the clock waveform, it is very easily filtered. Another type of noise, called analog noise, is
more difficult to filter since it is usually produced randomly from sources outside the logic
system. The filtering of analog noise will not be discussed in this text.

Which Methods Should Be Used to Eliminate a Potential ORG? If possible, make the
proper choice of don't-care values in output K-maps or change the state code assignments as
needed to eliminate ORGs. These two reliable methods are least likely to increase hardware
requirements and slow down FSM operation. Choosing the output hardware in accordance
with Fig. 10.18 is somewhat "iffy," since this method may depend on a single gate delay
to force branching along a particular non-ORG race path (see Fig. 11.4.). Unlike methods
1 and 2, method 3 does not offer assurance that a given ORG will not form.
Methods 4 and 5 both involve delays in the performance of the FSM and in most cases
increase the hardware requirements. The filter method (4) is the most desirable of the two,
since only a half CK cycle (plus the path delay through the D flip-flop) is involved. The
filter method also has another advantage. By using a bank of such flip-flops (called an
output holding register) to filter multiple outputs from an FSM, the outputs can be delivered
synchronously to the next stage. Use of a buffer state (5) to eliminate a race condition in
a branching path (one that caused the ORG) introduces an additional clock cycle in that
branching path, and this may not be an acceptable option.
Least desirable, usually, is method 6. Although increasing the number of state variables
may not alter the performance appreciably, this method does require an additional flip-flop
and additional feedback paths for each state variable that is added. Thus, method 6 usually
requires additional NS logic and may even require additional output-forming logic. The
one-hot code method, discussed in Section 13.5, offers some advantages over conventional
coding methods, but at the expense of requiring as many state variables (hence, also flip-
flops) as there are states in the state diagram (see Table 2.11).

11.3 DETECTION AND ELIMINATION OF STATIC HAZARDS
IN THE OUTPUT LOGIC

A detailed treatment of static hazards in combinational logic circuits is provided in Sections
9.1 and 9.2 and forms the basis for discussion of hazards in the output logic of FSMs
presented in this section. It is recommended that the reader review these sections before
continuing on in this section. Unique to state machines is the fact that the static hazards can
be either externally initiated (as in combinational logic) or internally initiated because of