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11.3 DETECTION AND ELIMINATION OF STATIC HAZARDS 503

placed within that from the ORing operation by an amount equal to the path delay through a
gate. From this information the following conditions for s-hazard formation can be stated:

• Conditions for static 1-hazard (SOP hazard) formation:
1. A 1 -> 0 change in the Q output of the flip-flop when <2(H) leads Q(L)
2. A 0 -» 1 change in the Q output of the flip-flop when Q(L) leads Q(H)
• Conditions for static 0-hazard (POS hazard) formation:
3. A 0 -* 1 change in the Q output of the flip-flop when Q(H) leads 0(L)
4. A 1 -> 0 change in the Q output of the flip-flop when Q(L) leads <2(H)

Note that these four conditions are similar to those for combinational logic when considering
the activation level of the initiating (coupled-variable) input. In Figs. 9.2 and 9.3, for
example, the coupled-variable inputs to the SOP logic circuits are the external inputs A(H)
and A(L), respectively. For internally initiated s-hazard formation, the coupled-variable
input is assumed to be the output from a basic cell, Q(H) and Q(L). This is a valid assumption
since the output stage of the most common flip-flops is a basic cell with mixed-rail outputs.
By relating the mixed-rail output response of the basic cells to the conditions for s-
hazard formation just stated, two useful conclusions can be drawn. To understand how
these conclusions come about, it is necessary to revisit Fig. 10.18. Presented in Fig. 11.12
are the mixed-rail output responses of the basic cells together with the conditions for s-
hazard formation for each, as deduced from conditions 1 through 4 previously stated. An
inspection of Fig. 11.12a reveals that the mixed-rail output response for the set-dominant
(SOP) basic cell generates the conditions for POS hazard (static 0-hazard) formation. In
dual fashion, the mixed-rail output response for the reset-dominant (POS) basic cell in
Fig. 11.12b generates the conditions for SOP hazard (static 1-hazard) formation. That the
set- and reset-dominant basic cells can be called SOP and POS circuits, respectively, is
easily deduced from an inspection of Figs. 10.1 la and 10.13a.
From Fig. 11.12 and the forgoing discussion, the following two conclusions can be
drawn, subject to the assumption that the coupled variables in an output expressions are
state variables produced from the mixed-rail outputs of the flip-flops:

• For flip-flops with NAND-centered (SOP) basic cells, s-hazards produced by
either al->OoraO—>• 1 change in the coupled variable are not possible if SOP
output logic is used.
• For flip-flops with NOR-centered (POS) basic cells, s-hazards produced by either
aO-> 1 or a 1 -> 0 change in the coupled variable are not possible if POS output
logic is used.

The ramifications of the forgoing conclusions are important in FSM design. If the output
logic and that for the basic cell output stage of the flip-flop are matched, that is, both SOP
or both POS logic, internally initiated s-hazards are not possible in the logic domain. For
example, if the output logic of an FSM is to be implemented by using an SOP device, such as
a PLA, the choice of NAND-centered flip-flops avoids the possibility of internally initiated
s-hazard formation in the output logic of that FSM. On the other hand, if the form of the
output logic and that for the basic cell of the flip-flops are different, one SOP and the other
POS, s-hazards are possible on either al—»-OoraO-> 1 change of the coupled variable (state