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14.2 THE LUMPED PATH DELAY MODELS FOR ASYNCHRONOUS FSMS 685

14.1.2 Need for Asynchronous FSMs
It is perhaps natural to believe that the data processing in and passage through a sequen-
tial machine must be regulated by some periodic sampling (enabling) function, the system
clock. This, of course, is a requirement of the synchronous sequential machine. But one never
questions the absence of a clock in the combinational logic circuits covered in Chapters 6,
7, and 8, yet these circuits are asynchronous machines of a type — those without feed-
back (i.e., nonsequential). Why then the concern about the need for a clock to regulate
synchronous sequential operations? And when is it advantageous, if ever, to perform se-
quential operations asynchronously? The complete answers to these questions will be
forthcoming, but only after most of the contents of this chapter has been considered. For
now let it suffice to say that it may be desirable to use asynchronous designs for the following
reasons:

• The speed requirements of the system may exceed the capability of synchronous
machines. Properly designed, a synchronous FSM can only approach (not equal)
the speed of a properly designed asynchronous FSM performing the same se-
quential operation(s). There are exceptions to this rule.
• Use of a system clock to synchronize a given sequential machine may not be pos-
sible or even desirable. Clock distribution problems (clock skew) may seriously
limit the use of synchronous designs, particularly in complex digital systems
operated at very high frequencies.
• Since flip-flops and clock oscillator circuits are absent, an asynchronous design
may occupy less real estate on an 1C chip and use less power than an equiv-
alent synchronous design. However, this statement may not be true for com-
plex asynchronous FSMs, the components of which must communicate through
handshake configurations.
• Just as there are some designs that should be carried out synchronously, there are
other designs that lend themselves quite naturally to asynchronous design. This
statement may be even more relevant in integrated systems, systems containing
both synchronous and asynchronous state machines, where maximum speed is
required.

Clearly, there is potential for use of asynchronous machines. In fact, it is predictable
that designers will become more familiar with this type of machine, that asynchronous
design techniques will improve, and that asynchronous FSM methods will play an impor-
tant role in the design of future superhigh-speed microprocessors and computers. It is the
judgment of many digital designers that the continued upward climb of system size and
speed will require more integration of asynchronous FSMs into "conventional" system-level
designs.

14.2 THE LUMPED PATH DELAY MODELS FOR ASYNCHRONOUS FSMs

In synchronous FSMs the memory function is formed by using flip-flops. But if asynchro-
nous FSMs are characterized by the absence of such devices as flip-flops, how, then, does