Page 716 - Engineering Digital Design

682 CHAPTER 13 / ALTERNATIVE SYNCHRONOUS FSM ARCHITECTURES

Controller Outputs: FR = Farm Red; FG = Farm Green; FY = Farm
Yellow; HR = Highway Red; HG = Highway Green; HY = Highway
Yellow; S30 = Start 30 seconds; S5 = Start 5 seconds; LDCNT =
Load counters

Use a minimum number of RET D flip-flops and an optimum NS and output
logic for the controller. Pay particular attention to timer requirements as they per-
tain to the handshake interface, counter design, and clock frequency. To do this,
construct timing diagrams if necessary. Initialize the system properly and deal with
any asynchronous input requirements. Assume that the clock frequency is 13.1
kHz.
Hints and suggestions:
(1) Six or seven states are adequate for the state diagram.
(2) Plan to synchronize inputs and filter outputs as needed.
4
(2) Use divide-by-16 and divide by 16 parallel loadable binary counters to gen-
erate the 5 second and 30 second time intervals. Counters will need to be
initialized.
(3) Counter design should follow that in Figs. 12.19, 12.20, and 12.21.
(4) By law, a green light never changes directly to red, but must first change to
yellow.
(5) Assume that mechanisms for light generation exist and that they are unaffected
by logic noise.
(6) The output LDCNT must be free of logic noise.

13.22 At the discretion of the instructor, use the software A-OPS (see Appendix B) in-
cluded on the CD-ROM bundled with this text to work any of the following one-hot
approach problems and include their VHDL descriptions: 13.15, 13.16, 13.17,
13.18. A readme.doc accompanying this software explains its use. Note that an as-
signment 13.22/13.16a would require the use of the A-OPS software to work only
circuit (a) of Problem 13.16. If necessary, refer to Section 16.4 for more information
regarding one-hot programmable sequencers and their use.