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take up more than 40 percent of a mobile phone printed circuit board. This will only
increase as integration of functions such as Bluetooth, wireless LAN, and GPS are
included. While integrating such components on a bipolar CMOS (BiCMOS) process is
possible, it cannot match up with the aggressive yield and test cost goals of high-volume
applications such as mobile phones. Integration in advanced BiCMOS processes such as
SiGe is possible, but typically this technology is one or two process nodes behind the
digital process technology.
While CMOS will continue to be the technology of choice for mobile applications,
work continues to be needed to address the challenges of keeping up with other
alternatives like bipolar technologies (SiGe) in terms of power efficiency and high
performance for mixed-signal and RF components, or GaAs processes for power
amplifier circuits that all go into a wireless system. Packaging advances will also
influence this roadmap moving forward since system-in-package (SIP) and system-on-
package (SOP) approaches are fast becoming viable solutions for integrating RF
components on a single package rather than on the same die. Breaking the functionality
into separate digital and analog components provides the flexibility of rapidly shrinking
the SOC devices without getting locked into the shrinking constraints imposed by the
analog circuits.

2.5 Summary
In this chapter we presented system-on-chip (SOC) as a way to provide a customized
optimal solution for various electronics systems of the Internet era. We discussed key
customer requirements and showed how by moving from multiple chips on a board to
a single-chip solution, SOCs address the application requirements. Such levels of
integration are made feasible by advances in CMOS manufacturing technology.
However, with these advances come design challenges too—in terms of verification
and testing of these complex systems, which include software running on embedded
processors, and also in terms of chip create and design implementation, which
maximizes technology entitlement in the presence of deep submicron silicon effects. We
highlighted these design challenges and presented approaches to address them.
While CMOS scaling enables increasing levels of integration, single-chip integration
may not always be the most optimal solution. This is true for heterogeneous systems
that require analog, RF, flash memory, and power management type of components
along with digital blocks. Analog design, for example, is not able to leverage CMOS
scaling as aggressively as the digital blocks, and in terms of system cost for a given
power and performance requirement, an appropriate partition of the system across
multiple chips using the SOP concept may provide a better solution.

References
1. “International Technology Roadmap for Semiconductors (ITRS)—2004 Update,”
http://www.itrs.net/Links/2004Update/2004Update.htm.
2. Vijay K. Madisetti and Chonlameth Arpikanondt, A Platform-Centric Approach to
System-on-Chip (SOC) Design, Springer, 2005.
3. Henry Chang et al., Surviving the SOC Revolution—A Guide to Platform-Based Design,
Kluwer Academic Publishers, 1999.
4. Rochit Rajsuman, System-on-a-Chip: Design and Test, Artech House, 2000.