Page 95 - System on Package_ Miniaturization of the Entire System

Intr oduction to System-on-Chip (SOC) 71

from the interconnect is continuously increasing. This makes timing estimation
a very critical component of design planning. Traditional approaches to
estimating the interconnect delay were based on the concept of wire-load
models (WLM). These models are statistically generated and provide an
estimate of the parasitics of the wire in relation to fanout, and therefore can be
used to estimate the delay of the interconnect wire on the chip. However, this
approach has long been replaced by more realistic interconnect delay calculation
models and methods. Given the several process and scaling effects discussed
earlier, the RC parasitics of the wire depend on a lot more factors than just
fanout; hence, a WLM was considered grossly inaccurate to model these effects.
Inaccuracies in such estimates caused timing surprises later during physical
implementation, and therefore poor convergence in the design flow. The
criticality of the physical aspects impacting the circuit and interconnect delays
such as the wire length, coupling capacitance between neighboring wires, and
clock signal skews require access to a lot more physical implementation
information to reasonably estimate interconnect delays. This pioneered the
advent of the physical synthesis technology where the underlying logic
synthesis and placement of the SOC components occurred concurrently, thereby
providing a lot more accuracy in delay estimation and hence a lot more
confidence in the timing feasibility of the design. In addition to the delay
estimation, the timing feasibility of the SOC implementation also depends on
the design and IP constraints that drive the timing optimization. Design
planning also involves verifying the timing specification of the SOC by
validating these constraints and budgeting the top-level constraints among the
several soft and firm IPs being integrated on the SOC. Timing abstractions of
hard IPs are used during this process.
• Routability estimation. The process of determining whether the original SOC
physical size estimation is sufficient to achieve design closure is done by an
interconnect wire routing resource availability versus demand analysis, also
called congestion analysis. Given the original floor plan, timing, and other
physical constraints, budgets for various soft IP and physical and timing
abstractions for the hard IP, a quick power grid distribution, and global
placement are done. This global placement is then used as a starting point to
virtually route all interconnects between the components keeping in mind the
timing or other constraints fed in. This virtual route is a pretty good estimate of
the availability and demand for routing resources to ultimately connect up the
SOC components, and hence is a good measure of routability. Congestion “hot
spots,” if any, are tweaked by placement changes and another design planning
iteration done to verify the SOC design goals.

Hierarchical SOC Design
As the thirst for modern electronics continues to require larger levels of logic integration
on a single chip, it is not uncommon to see SOC designs with over 10 to 20 million gates
required to be integrated. This poses significant complexity and challenges through the
SOC “create” flow, requiring a divide-and-conquer approach to attacking the problem.
Design planning and implementation of such large SOCs is enabled using a hierarchical
design methodology as shown in Figure 2.23. The basic principle of hierarchical design
is to use the design planning framework described above to break the SOC implementation