Page 94 - System on Package_ Miniaturization of the Entire System

70 Cha pte r T w o

feasibility, thereby validating the original decisions. This iterative process continues
until the “implementation prototype” is refined sufficiently such that the confidence of
committing to the original decisions is extremely high. The obvious challenge in the
above methodology is the “quick” versus “accurate” contradiction, and the success of
design planning wholly depends on the quality of the involved tradeoffs. Following are
some of the SOC design planning activities that fall into this input-estimate-refine
process:
• Floor planning. The first step in design planning is to physically plan the
components on the SOC. This involves defining the areas on the die that will be
occupied by the incoming hard IP, memory blocks, mixed-signal or other
custom blocks, and external I/O cells. An initial placement of these components
is arrived at based on basic connectivity information between them and forms
the original “forced” baseline to estimate the overall size, timing, power, and
other factors to check for physical feasibility. Based on the estimates obtained,
this original floor plan can be refined or tweaked until there is good confidence
in achieving critical goals such as the die size (or area), timing, and power.
• Size estimation. This process involves calculating the minimum silicon area that
would be required to accommodate all the components (logic, memory, I/O
cells, IP blocks, interface logic, other special macros, etc.) and the amount of
interconnect wire required to connect up all these components. The SOC
specification drives the selection of appropriate memory configurations, I/O
choices, and the physically ready IP blocks required. Given that this reuse is
occurring in the “hard” form, estimating the size of these components is fairly
trivial. Estimating the logic area is not as straightforward and requires a decent
estimate of the amount of logic to be integrated along with a targeted logic
density achievable for that particular logic library and process technology.
Estimating the interconnect wiring area requires using a routing efficiency
factor that represents the overhead associated in connecting up all the above
components meeting the design rules. Other contributions that are typically
considered overheads arise from the physical power grid distribution required
on-chip to meet the SOC power and performance goals as well as any other
special spacing careabouts during physical integration to address issues such as
noise, crosstalk, and other such effects.
• Power estimation. Given that several SOC applications such as mobile handsets
and portable appliances require a very tight control over the power that is
dissipated, early estimation of power is crucial right from the SOC architectural
or system level. This level has the largest impact on making the right level of
tradeoffs to reduce the power either in terms of tweaking the application
algorithms or in deciding the need for voltage scaling to address power. Once a
technology node and library are selected for the SOC implementation, power
estimation is done by determining the amount of switching logic and the
switching activity per block. Switching activity information can come from
vectors generated by application test cases that represent worst-case SOC
working operation.
• Timing estimation.Given the fact that metal resistance per unit length is increasing
with scaling, while gate output resistance is decreasing, and compounded by
the fact that average wire lengths are not coming down, the delay contribution