Page 98 - System on Package_ Miniaturization of the Entire System

74 Cha pte r T w o

placement and routing is therefore critical to avoid such signal integrity issues while
timing optimizations are being done. Note the concurrent nature of the solution that
this demands. Aggressive scaling of interconnect wires is also increasing the resistance
per unit length of these wires and the average current densities. With logic switching at
high speeds as well, depending on the magnitude of the current flowing in the power
grid and the length, width, and sheet resistance of the power grid, the actual voltage as
seen by the switching logic can be much less than the true supply voltage. This slows
down the transistor performance characteristics and hence can cause a timing violation
in the circuit. This problem can be overcome by designing a robust power grid on the
SOC in such a way that a minimum voltage level is guaranteed across the chip, and
then ensuring that the performance of the device is met at that voltage. However, as
evident, since not all switching logic in an SOC are equally timing critical, this can cause
overdesign of the power grid, and hence over-constrain the routing resources required
to ensure the SOC routability and area goals are met. Again, note the concurrent nature
of the optimizations needed to achieve overall design closure, as defined earlier. Another
critical phenomenon in the presence of high interconnect current densities and high-
speed SOC components is the signal or power electromigration problem. The migration
of metal ions due to the electron wind caused by the current causes voids (opens) or
hillocks (shorts) between neighboring interconnect wires, thereby potentially causing
functional failures. A common solution to the electromigration problem is to increase
the width of the interconnect wires or add more vias to the power grid, again impacting
the total routing resources available. Electromigration is not an initial time phenomenon,
in the sense that while the device will function at the time it is manufactured, the longer-
term life of the device operation is at risk due to these reliability issues. Design closure
for SOC designs is therefore a multi-optimization problem, and an integrated approach
is required to address all the careabouts. Also critical from a time-to-market perspective
is a methodology where the above signal integrity and reliability issues can be avoided
during the physical design process as opposed to addressing or fixing them as an
afterthought and thereby incurring painful iterations and increased cycle times.
Mixed-Signal Integration
One of the recent challenges in SOC design has been the integration of complex digital
circuitry and analog or RF components on the same chip. This has been necessitated by
the ever-increasing demand for applications such as wireless handsets, WLAN products,
single-chip satellite TV setup boxes, and Bluetooth-enabled products. Integrated mixed-
signal components could be high-performance phase locked loop (PLL) blocks, high-
speed I/O interfaces, RF modules, or high-speed and high-resolution analog-to-digital
converters (ADCs) and digital-to-analog converters (DACs). The substrate is the
connecting layer between all circuits in a single piece of silicon. Thus when high-speed
digital switching components inject noise or produce spiky signals, they get injected
into the common substrate. This noise can impact the sensitive analog circuitry on the
same chip. Further complicating the issue is the technology scaling trends that allow
higher frequency and reduced voltage of operation as shown in Figure 2.26. All these
issues have resulted in silicon failures or reduced yields for such mixed-signal, RF-
integrated SOC designs.
The key contributor of the digital noise that gets injected into the substrate in the
SOC context is the power supply, given that the CMOS core and I/O logic cause spikes
on the supply lines which in turn are connected to the substrate. The other significant
contributor is the package bond wire inductance (L) that can increase the L di/dt noise