Page 90 - System on Package_ Miniaturization of the Entire System

66 Cha pte r T w o

particularly in the microprocessor space, is to go for multiple CPU engines, popularly
called the “dual-core” architectures, where multiple CPU cores are integrated in silicon
on the same die. This provides additional flexibility to manage and distribute power,
particularly as options to reduce operating voltages and performance become an option.
Dual-core processor architectures allow devices to run multiple “threads” at a time and
are therefore amenable to what is referred to as thread-level parallelism. Additionally,
integrating multiple CPU cores on a single die improves the performance of the circuits
since the signals do not have to travel off-chip, and also utilize the board space in the
system more efficiently compared to two discrete chips. Even in the digital signal
processor SOC world, integrating a RISC digital signal processor with a microcontroller
such as ARM or MIPS is very common, and the DSP functions are available as hardware
accelerators.
With process nodes at and below 90 nm, in-die variations are becoming a huge issue
to tackle, placing SOC manufacturability at risk. If in-die variations and their effects are
not modeled correctly, there is a large probability of silicon failure causing mask respin
and hence an increased cost. The width variation of a critical wire in layout depends on
the width of the wire segment and the spacing to its neighbor. This variation is referred
to as selective process bias (SPB). Resistance and Capacitance (RC) extraction engines
use a two-dimensional table of width and spacing to model these wire width variations.
Design experts now talk about hold failures found on silicon attributed back to metal
RC variation between adjacent planes. Given that recent SOC design can support seven
to eight metal layers, it becomes computationally prohibitive to use traditional analysis
tools to comprehend these effects. At the same time, the traditional single (typically
worst-case) corner timing analysis approach is no longer sufficient to handle such in-
die or intrachip variations. Hence statistical timing analysis methods and variation-
aware timing closure flows are being investigated for 90-nm and below SOC designs.
Another increasingly threatening device reliability or, as it is commonly referred to,
“chip aging” issue, is the negative bias temperature instability (NBTI), specifically
occurring at lower operating voltages. NBTI is known to cause significant V shifts, and
t
hence an accurate method to model this effect is required.
Traditionally, yield has been considered a fabrication-only issue. The manufacturability
issues of an SOC were limited to the adherence of design rules that the FAB would drive
for a particular process. With design feature sizes and spacing rules getting lower than
the wavelength of light, process material and lithography effects can considerably alter
what gets created by the layout designer versus what gets actually printed on silicon.
This, in effect, changes the electrical characteristics of the circuit causing reliability or
speed problems. As a result, physical designers need to understand these manufacturing
effects and up-front handling of the impact during layout and analysis. This trend is
similar to what happened 5 to 10 years back with logic and physical design merging to
attack the timing closure problem. Chemical and mechanical polishing (CMP) has been
a well-known step during manufacturing to ensure planarization of the silicon surface
and hence improve yield. However, this can cause changes in the thickness of the
dielectric between metal layers and interconnect resistance, and therefore impact die
yield. This problem can be circumvented by postprocessing the layout with strips of
dummy metal to even out the metal density on the chip. Insertion of dummy metal can,
in turn, impact the timing of critical signals on the chip and can even cause additional
parasitic coupling to existing signals that could result in functional problems. Layout
designers should, therefore, comprehend the effect of such dummy fill insertion during
placement and routing and ensure timing analysis considering the impact of these