Page 173 - System on Package_ Miniaturization of the Entire System
P. 173

148    Cha pte r  T h ree


                      64.  Tru-Si Technologies, “Through-silicon vias” available on http://www.trusi.com/frames.
                        asp?5 (Access date: Dec. 4, 2007)
                      65.  K. Takahashi et al., “Development of advanced 3D chip stacking technology with
                        ultra-fine interconnection,” Proc. 51st Electronic Components and Technology Conference,
                        2001, pp. 541–546.
                      66.  V. Kripesh et al., “Three dimensional stacked modules using silicon carrier,” Proc.
                        2003 Electronics Packaging Technology Conference, 2003, pp. 24–29.
                      67.  N. Tanaka et al., “Ultra-thin 3D-stacked sip formed using room-temperature bonding
                        between stacked chips,” Proc. 2005 Electronic Components and Technology Conference,
                        2005, pp. 788–794.
                     68.  PhysOrg, “Samsung Develops 3D Memory Package that Greatly Improves
                        Performance Using Less Space” available on http://www.physorg.com/news64161294.
                        html (Access date: Dec. 4, 2007)
                     69.  S. Vangal et al., “An 80-tile 1.28 TFLOPS network-on-chip in 65nm CMOS,” Solid-State
                        Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International,
                        2007, p. 98.
                      70.  IBM Corporation, “SiGe BiCMOS 5PAe: advanced through-silicon via technology for
                        RF power applications”, available on http://www-01.ibm.com/chips/techlib/techlib.nsf/
                        techdocs/6B994C8F42D91314002572E900707987/$file/5PAe_Aug2207_final.pdf (Access
                        date: Dec. 4, 2007)
                     71.  B. Swinnen and E. Beyne, “Introduction to IMEC’s research programs on 3D-
                        technology,” available on www.emc3d.org/documents/library/technical/IMEC%
                        20Technical%20Review_3D_introduction.pdf (Access date: Dec. 4, 2007)
                      72.  F. Niklaus, J.-Q. Lu, J. J. McMahon, J. Yu, S. H. Lee, T. S. Cale, R. J. Gutmann, “Wafer-
                        level 3D integration technology platforms for ICs and MEMs,” Proceedings of the
                        Twenty Second International VLSI Multilevel Interconnect Conference (VMIC), T. Wade
                        (ed.), IMIC 2005, pp. 486–493.
                      73.  A. Klumpp, P. Ramm, R. Wieland, and R. Merkel, “Integration Technologies for 3D
                        Systems” FEE 2006, May 17–20, 2006, Perugia, Italy. Available on www.mppmu.mpg.
                        de/~sct/welcomeaux/activities/pixel/3DSystemIntegration_FEE2006.pdf (Access date:
                        Dec. 4, 2007)
                      74.  J. U. Knickerbocker et al., “Development of next-generation system-on-package
                        (SOP) technology based on silicon carriers with fine-pitch chip interconnection,”
                        IBM J. Research and Development, vol. 49, no. 4/5, 2005, pp. 725–753.
                      75.  J. A. Burns et al., “A wafer-scale 3-D circuit integration technology,” IEEE Transactions
                        on Electron Devices, vol. 53, no. 10, 2006, pp. 2507–2516.
                      76.  H. Noh, Kyoung-sik Moon, A. Cannon, P. J. Hesketh, and C. P. Wong, Proc. IEEE
                        Electronic Components and Technology Conference, vol. 1, 2004, pp. 924–930.
                      77.  K. W. Guarini, A. W. Topol, M. Ieong, R. Yu, L. Shi, M. R. Newport, D. J. Frank,
                        D. V. Singh, G. M. Cohen, S. V. Nitta, D. C. Boyd, P. A. O’Neil, S. L. Tempest, H. B.
                        Pogge, S. Purushothaman, and W. E. Haensch, Proc. IEDM, 2002, pp. 943–945.
                      78.  M. Umemoto, K. Tanida, Y. Nemoto, and M. Hoshino, “High performance ver-
                        tical interconnection for high-density 3D chip stacking package,” Proc. Electronic
                        Components and Technology Conference ECTC, 2004, pp. 616 –623.
                      79.  K. N. Chen, A. Fan, and R. Reif, “Microstructure examination of copper wafer bond-
                        ing,” Journal of Electronics Materials, vol. 30, 2001, pp. 331–335.
                      80.  K.-N. Chen, S. H. Lee, P. S Andry, C. K. Tsang, A. W. Topol, Y.-M. Lin, J.-Q. Lu,
                        A. M. Young, M. Ieong, and W. Haensch, “Structure, design and process control for
   168   169   170   171   172   173   174   175   176   177   178