Page 169 - System on Package_ Miniaturization of the Entire System

144 Cha pte r T h ree

HDTVs would be a computing hub for a family that manages and controls all wireless
and wired digital data transmissions inside and outside of the home. The future
biosensors based on nano materials would find roles for personal security, health care,
and environment sensing.
All of these can be referred to as the next generation of miniaturization technologies.
In order to meet the above ever-increasing demands for miniaturization, a component
density of tens of thousands per cubic centimeter or a functional density that is about
100 to 1000 times more is required. The only way to achieve such parameters is by the
SOP concept at the system level as a follow-up to the SIP concept of stacked ICs at the
module level. One can project the SOP to consist of
• Ultrathin ICs of 3 to 10 μm in thickness
• Three-dimensional chip stacking of more than 100 memory and logic chips
• System wiring lines and spaces in the submicron range
• Through-silicon-via diameters and their pitch in the submicron range
One such SOP module was proposed by IBM [1], as illustrated in Figure 3.1. The
technology challenges to achieve the above goals include mixed-signal electrical design,
multifunction materials and processes, ultra high-density wiring, novel thermal
management of miniaturized systems, thermomechanical reliability, bumpless inter-
connections, mixed-signal testing and characterization, and low-cost manufacturing
technologies [94]. This book with its 13 chapters reviews the state of the art in all these
areas and predicts the next generation of technology evolutions in each.

Acknowledgments
The authors gratefully acknowledge the contribution of Robert M Nickerson, Nasser
Grayeli, and Johanna M Swann of Intel Corporation for their constructive and valuable
comments.

References
1. J. Knickerbocker, C. Patel, P. Andry, C. Tsang, L. Buchwalter, E. Sprogis, H. Gan,
R. Horton, R. Polastre, S. Wright, C. Baks, F. Doany, J. Rosner, and S. Cordes, “Three
dimensional silicon integration using fine pitch interconnection, silicon process-
ing and silicon carrier packaging technology,” IEEE 2005 Custom Integrated Circuit
Conference, pp. 659–662.
2. EIA/JEDEC Standard, JESD51-2: Integrated Circuits Thermal Test Method
Environment Conditions—Natural Convection (Still Air), December 1995.
3. EIA/JEDEC Standard, JESD51-6: Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air), March 1999.
4. EIA/JEDEC Standard, JESD51-8: Integrated Circuit Thermal Test Method
Environmental Conditions—Junction-to-Board, October 1999.
5. R. R. Tummala, E. J. Rymaszewski, and A. G. Klopfenstein (eds.), Microelectronics
Packaging Handbook, 3 vols.: Technology Drivers, Semiconductor Packaging, and
Subsystem Packaging, New York: Chapman and Hall, 1997.
6. J. P. Focarie, “Modular Circuit Assembly,” US Patent 3,459,998, 1969.