Page 170 - System on Package_ Miniaturization of the Entire System

Stacked ICs and Packages (SIP) 145

7. R. A. Jarvela, G. E. Lee, and J. W. Schmieg, “Stacked high-density multichip module,”
IBM Technical Disclosure Bulletin, vol. 14, no. 10, 1972, pp. 2896–2897.
8. D. J. McAtee, “Dual-in-line package socket piggyback structure,” IBM Technical
Disclosure Bulletin, vol. 16, no. 4, 1973, p. 1315.
9. P. A. Lutz, P. R. Motz, and E. H. Sayers, “Vertical integrated circuit package integra-
tion,” US Patent 4,398,235, 1983.
10. IBM Corporation, “Stackable J leaded chip carrier,” IBM Technical Disclosure Bulletin,
vol. 28, no. 12, 1986, pp. 5174–5175.
11. S. Savastiouk, O. Siniaguine, and E. Korczynski, “3-D stacked wafer-level packag-
ing,” Advanced Packaging, March 2000, pp. 28–34.
12. International Technology Roadmap for Semiconductors (ITRS), 2006 Update.
13. N. R Draney, J. Liu, and T. Jiang, “Experimental investigation of bare silicon wafer
warp,” IEEE Workshop on Microelectronics and Electron Devices, April 2005.
14. Larry Wu, Jacky Chan, and C. S. Hsiao, “Cost-performance wafer thinning technol-
ogy,” Proc. 53rd Electronic Components and Technology Conference, May 27–30, 2003,
pp. 1463–1467.
15. S. Sandireddy and T. Jiang, “Advanced wafer thinning technologies to enable
multichip packages,” Microelectronics and Electron Devices, 2005. WMED 2005 IEEE
Workshop on April 15, 2005, pp. 24–27.
16. C. Landesberger, S. Scherbaum, and K. Bock, “Carrier techniques for thin wafer
processing,” International Conference on Compound Semiconductor Manufacturing
Technology “GaAs Mantech,” May 14–17, 2007, pp. 33–36.
17. M. Yan, M. Bartlett, and B. Harnish, “UV Induced Attachment of Ultrathin Polymer
Films on Silicon Wafers,” Proc. 8th International Symposium on Advanced Packaging
Materials, March 3–6, 2002, pp. 311–316.
18. K. Bock, C. Landesberger, M. Bleier, D. Bollmann, and D. Hemmetzberger,
“Characterization of electrostatic carrier substrates to be used as a support for
thin semiconductor wafers,” International Conference on Compound Semiconductor
Manufacturing Technology “GaAs Mantech,” April 2005.
19. Disco Corporation, “Dicing Before Grinding (DBG) Process” available on http://www.
disco.co.jp/eg/solution/library/dbg.htm (Access date: Dec. 4, 2007).
20. J. Sillanp, J. Kangastupa, A. Salokatve, and H. Asonen, “Ultra short pulse laser
meeting the requirements for high speed and high quality dicing of Low-k wafers,”
Advanced Semiconductor Manufacturing Conference and Workshop, 2005 IEEE/SEMI,
April 11–12, 2005, pp. 194–196.
21. D. Perrottet, S. Green, and B. Richerzhagen, “Clean dicing of compound semi-
conductors using the water-jet guided laser technology,” 17th Annual SEMI/IEEE
Advanced Semiconductor Manufacturing Conference, 2006, ASMC, May 22–24, 2006,
pp. 233–236.
22. Amkor Technology, “Stacked CSP (LFBGA/TFBGA / SCSP) Data Sheet” available
on http://www.amkor.com/products/all_datasheets/SCSp.pdf (Access date: Dec. 4, 2007)
23. E. J. Vardaman, “Trends in 3-D packaging” available on http://www.napakgd.com/previous/
kgd2004/pdf/vardaman.pdf (Access date: Dec. 4, 2007).
24. J. Demmin, “Packaging beat: Industry leaders vie for memory-stacking bragging
rights,” Solid State Technology, available on http://sst.pennnet.com/articles/article_display.
cfm?Section=ARCHI&C=TETAK&ARTICLE_ID=295133 (Access date: Dec. 4, 2007).
25. K. M. Brown, “System in package the rebirth of SIP,” Proc. IEEE Custom Integrated
Circuits Conference, 2004, Oct. 3–6, 2004, pp. 681–686.