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Stacked ICs and Packages (SIP)      147


                      46.  C. W. C. Lin, S. C. L. Chiang, and T. K. A. Yang, “3D stacked high density packages
                        with bumpless interconnect technology,” IEEE Nuclear Science Symposium Conference
                        Record, vol. 1, Oct. 19–25, 2003, pp. 73–77.
                     47.  K.-F. Becker, T. Braun, A. Neumann, A. Ostmann, M. Koch, V. Bader, R. Aschenbrenner,
                        H. Reichl, and E. Jung, “Duromer MID technology for system-in-package genera-
                        tion,” IEEE Transactions on Electronics Packaging Manufacturing, vol. 28, no. 4, 2005,
                        pp. 291–296.
                      48.  C. Val, “Three dimensional interconnection method and electronic device obtained
                        by same,” US Patent 6,716,672 B2, 2004.
                      49.  M. Karnezos, “Package-in-package: A 3-D stacked package module,” 11th Annual
                        International KGD Packaging and Test Workshop, September 12–15, 2004, available
                        on http://www.napakgd.com/previous/kgd2004/pdf/karnezos.pdf (Access date: Dec. 04,
                        2007).
                     50.  Intel Corporation, “Packaging Overview” available on http://download.intel.com/design/
                        flcomp/packdata/wccp/download/chpt1.pdf (Access date: Dec. 04, 2007).
                     51.  Tessera Technologies, “Folded die stack” available on http://www.tessera.com/technologies/
                        products/z_mcp/folded_stacked.htm (Access date: Dec. 04, 2007).
                      52.  T. Yamazaki, Y. Sogawa, R. Yoshino, K. Kata, I. Hazeyama, and S. Kitajo, “Real chip
                        size three-dimensional stacked package,” IEEE Transactions on Advanced Packaging,
                        vol. 28, no. 3, 2005, pp. 397–403.
                     53.  Y. Yano, T. Sugiyama, S. Ishihara, Y. Fukui, H. Juso, K. Miyata, Y. Sota, and
                        K. Fujita, “Three-dimensional very thin stacked packaging technology for SiP,”
                        Proc. 52nd Electronic Components and Technology Conference, May 28–31, 2002,
                        pp. 1329–1334.
                      54.  T. Matthias et al., “3D process integration—wafer-to-wafer and chip-to-wafer bond-
                        ing,” Mater. Res. Soc. Symp. Proc., vol. 970, 2007, p. 0970-Y04-08.
                      55.  A. D. Scarbrough, “3D-coaxial memory construction and method of making,” US
                        Patent 3704455, 1972.
                      56.  T. R. Anthony, “The random walk of a drilling laser beam”, Journal of Applied Physics,
                        vol. 51, 1980, p. 1170.
                      57.  T. R. Anthony and P. A. Lindner, “The reverse laser drilling of transparent materials,”
                        Journal of Applied Physics, vol. 51, 1980, p. 5970.
                      58.  T. R. Anthony, “Forming electrical interconnections through semiconductor wafers,”
                        Journal of Applied Physics, vol. 52, no. 8, 1981, pp. 5340–5349.
                      59.  J. F. McDonald et al., “Multilevel interconnections for wafer scale integration,”
                        Journal of Vacuum Science & Technology A (Vacuum, Surfaces, and Films), vol. 4, no. 6,
                        1986, pp. 3127–3138.
                      60.  F. Laermer and P. Schilp, “Method of anisotropically etching silicon,” U.S. Patent
                        5501893, 1994.
                      61.  C. Christensen, P. Kersten, S. Henke, and S. Bouwstra, “Wafer through-hole intercon-
                        nections with high vertical wiring densities,” IEEE Trans. Components, Packaging and
                        Manufacturing Technol. A, vol. 19, 1996, pp. 516–522.
                      62.  P. Kersten, S. Bouwstra, and J. W. Petersen, “Photolithography on micromachined
                        3D surfaces using electrodeposited photoresists,” Sensors and Actuators A, vol. 51,
                        1995, p. 51–54.
                      63.  J. Gobet et al., “IC  compatible fabrication of through-wafer conductive
                        vias,” Proceedings of the SPIE—The International Society for Optical Engineering,
                        vol. 3223, 1997, pp. 17–25.
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