Page 33 - Sami Franssila Introduction to Microfabrication

12 Introduction to Microfabrication

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area to A/N . Gate width, gate oxide thickness and Integrated circuit wafers contain typically a hundred
source/drain-diffusion depths are closely related, and the or hundreds of chips (also called die), Figure 1.13. This
ratios are more or less unchanged when transistors are number has remained more or less unchanged over
scaled down. As a rough guide, for gate length of L, decades because chip size and wafer size have grown
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oxide thickness is L/45, and source/drain junction depth in parallel: 0.2 cm chips were made on 100 mm wafers
is L/5. while 2 cm 2 chips are usual on 300 mm wafers. In
extreme cases, only one chip fits the wafer, for example,
a solar cell, a thyristor or a position-sensitive radiation
1.10 CLEANLINESS AND YIELD detector. Microfluidic separation devices with 5 cm long
channels and optical waveguide devices with large radii
Microfabrication takes place under carefully controlled of curvature can have a handful of devices per wafer.
conditions of particle purity, temperature, humidity and With standard logic chips or with micromechanical
vibration because otherwise micrometre scale structures pressure sensors, thousands can be crammed to fit into
would be destroyed by particles or else lithography a wafer.
process would be ruined by vibrations or temperature
and humidity fluctuations. Two cleanroom designs are
shown in Figure 1.12: high-efficiency filters can be 1.11 INDUSTRIES
placed locally or they can have 100% coverage, offer-
ing improved cleanliness and laminar (unidirectional) The electronics industry is based on semiconductor
airflow. Wafers are cleaned actively during processing: devices, which are based on silicon.
hundreds of litres of ultrapure water (de-ionized water, In 2002, ca. 10 18 transistors were shipped, some
DIW) are used for each wafer during its fabrication. This 150 million for each and every human on earth. As
is the dynamic part of particle cleanliness: the passive recently as 1968, it was one transistor per year per
part comes from careful selection of materials for clean- person. The price, of course, explains a lot: in 1968,
room walls, floors and ceilings, including sealants and transistors cost ca. $1 a piece; in 2002, the cost was
paints, plus process equipment, wafer storage boxes and $0.000 0001.
all associated tools, fixtures and jigs. Worldwide, about $6 billion is spent on silicon wafers
Even though extreme care is taken to ensure cleanli- annually. These are used to make $150 billion worth
ness during microprocessing, some devices will always of semiconductor devices, which fuel the 1000 billion
be defective. As the number of process steps increases, electronics industry. Other related businesses include
n
the yield goes down as Y = Y , where Y o is the yield the $25 billion semiconductor manufacturing equipment
o
of a single process step and n is the number of steps. industry and the $15 billion materials industry (which
With 100 process steps and 99% yield in each indi- includes for example chemicals, gases, photomasks and
vidual step, this results in 37% yield (representative sputtering targets).
of 64 kbit Dynamic random access memory (DRAM) Microsystems industry as such does not exist:
chip) but 99% yield for a 500 step process (representa- microsystems are rather a technology more than an
tive of 16 Mbit DRAM) results in <1% yield. Clearly, industry; therefore, statistics are erratic. Some estimates
99% yield is not enough for modern memory fabri- put microsystems sales at $13 billion (2000), but this
cation. Chip design also affects yield through area: presents module prices (e.g., ink-jet cartridge; not just
Y = exp(−DA) where A is chip area and D is the defect the silicon nozzle chip). Chip sales might be 10% of
density: making small chips is much easier than making module prices, because microsystems packaging and
big chips. testing are very complex. The flat-panel displays indus-
Yield has two major components: stochastic and sys- try has sales of some $23 billion in 2000. It has more
tematic. Stochastic (random) defects are unpredictable and more of its own suppliers for process equipment,
occurrences of pinholes in protective films, particle and of course, for the glass plates used as substrates.
adhesion on the wafer, corrosion of metal lines, and Device density on chips is quadrupling in three-year
so on. Systematic defects come from equipment and intervals, a trend known as Moore’s law. Scaling has
operator failures, impurities in starting materials and continued relentlessly for the past 40 years. Linewidths
design errors: two features are placed so close to each were in the 30 µm range in early 1960s, and they are
other that they will inadvertently touch, or impurities 0.18 µm in the year 2000. Lithographic scaling has
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in chemicals do not allow low enough leakage cur- thus improved packing density by a factor (30/0.18) ≈
rents. 30 000. The number of transistors on a chip has