Page 166 - Mechatronic Systems Modelling and Simulation with HDLs

7.5 DEMONSTRATOR 4: DISK DRIVE 155

• Spindle control
The spindle control detects the current rotational velocity, e.g. by means of
6
back-emf evaluation of the undriven phase of the brushless DC spindle motor.
This information is taken into account in the control of the rotational veloc-
ity of spindle and disk stack. Spindle control also includes the (electronically
controlled) commutation of the motor’s phases and the implementation of
sophisticated start-up algorithms. The problem with the start-up is that the
brushless DC motor has no preferred rotation direction. However, if the disk
rotates in the wrong direction the read/write-head might easily damage the
disk’s surface. So a great deal of work is underway into the sequence of the
spindle motor start-up commutation to reliably provide for the correct rota-
tion direction.
• Signal processing
The signal processing function controls the data as it is written to and read
from the disk. It encodes the data to be stored, and writes it to the read/write-
head. When reading from the read/write-head, the data is pre-amplified and
retrieved, using sophisticated techniques like the partial response maximum
likelihood method. To allow for even more density — i.e. an even worse signal
to noise ratio — the data on the disk contains additional information which is
used for error correction. This often is based on Reed/Solomon techniques.

• Buffer management
Data written to or read from the disk has to be fed through a buffer of substantial
size to reliably rule out over- and under-runs. For this, DRAM of typically
0.5–2 MBytes is employed, which may be stand-alone or embedded in a system
on a chip. In addition, a buffer manager is necessary that offers caching facilities
and manages access to the memory for data buffering and other purposes, e.g.
program execution from the DRAM.

• Host interface
The host interface implements the communication with the host computer. It
interprets the IDE or SCSI commands given and arranges their completion.

In the design process these functions are mapped to an architecture. The list
of functions and the overall architecture is more or less generic and is the same
for most of the disk drive designs, see Figure 7.14. The overall architecture of the
disk electronics is based on five circuits, see Figure 7.14: motion-control, hard disk
controller (HDC), RW-channel (stand-alone or embedded), pre-amp and DRAM
(stand-alone or embedded). The HDC provides the micro-controller and also looks
after the host interface and — together with the DRAM — the buffer management.
The RW-Channel — together with the pre-amp — incorporates the signal processing
function. Finally motion-control looks after the analogue and power side of servo

6 Electro-motive force.