Page 319 - A Practical Guide from Design Planning to Manufacturing

Semiconductor Manufacturing 289

Example CMOS Process Flow

This section shows how layering, photolithography, and etching steps are
used to create CMOS devices. Figures 9-19 to 9-32 show the masks used
and resulting cross sections of the die during each of the fabrication steps
of a generic CMOS process flow. For brevity, some steps have been left out,
but the major steps shown in this flow will be common to the fabrication
of most modern CMOS integrated circuits. The major steps shown are:
1. Shallow trench isolation
2. N-well implantation
3. P-well implantation
4. Poly gate formation
5. N-source/drain extension
6. P-source/drain extension
7. Sidewall formation
8. N+ source/drain implant
9. P+ source/drain implant
10. Silicide formation
11. Contact formation
12. Metal 1 (M1) wire creation
13. Via1 hole creation
14. Via1 and metal 2 (M2) wire deposition

The figure for each step (starting with Fig. 9-19) in the upper left shows
the mask (if any) used for patterning that step. For simplicity, any OPC or
PSM processing of the masks has not been included. The lower left shows
the processing in that step, specifically through a cross section labeled A.
The upper right shows the layout of the layers processed so far, and below
are shown the completed cross sections for that step along the A and B lines
labeled in the layout. The process steps are additive, with each subsequent
figure starting from the processed wafer of the previous figure.
The first step in creating transistors is to forming the insulation that
will separate the regions that will later hold N-type and P-type tran-
sistors. The LOCOS process can be used to grow thermal field oxide,
which will separate the active transistor regions; but to allow tighter
spacing between the different types of transistors, trenches are etched into
the silicon and filled with SiO using CVD. This is known as shallow
2
trench isolation (STI) to distinguish it from the deeper trenches that are
used in the fabrication of DRAM. See Fig. 9-19.
Layers of silicon nitride and then photoresist are deposited and pat-
terned. A dry etch cuts through the exposed silicon nitride and into the