Page 355 - A Practical Guide from Design Planning to Manufacturing

Microprocessor Packaging 325

least expensive solution a laminate substrate (MCM-L). These use FR4
layers and are manufactured just like a standard PCB. They may use bare
die applied to the board or already packaged die. As with single-die pack-
ages, a ceramic substrate (MCM-C) provides better thermal resistance at
higher costs. The most costly and highest performance solution is to use
thin film deposition and patterning techniques identical to those used on
die to build a deposited substrate (MCM-D). Many MCM packages will
combine these techniques by depositing thin buildup layers on top of thicker
core layers of FR4 or ceramic.
The scaling of Moore’s law means that any product that is less expen-
sive when produced as an MCM will in a short number of generations be
more cheaply produced as a single die. In the 0.6- and 0.35-µm technol-
ogy generations, processor frequencies reached high enough values that
two levels of cache memory were needed for good performance. However,
transistor dimensions were still large enough to make it impractical to
build a single die that contained the processor and all the cache memory.
This led to the use of MCMs, which allowed designs that would be too
expensive to fabricate as a single chip to be divided among several chips
while keeping the performance loss to a minimum. In later generations,
smaller device dimensions have allowed the level 2 caches and processor
to be built on a single die. New MCM solutions have followed where two
complete processor die are combined in one package. These are called
multichip processors (MCP). This is one way to implement a “dual-core”
processor, by packaging two-processor die together. As scaling continues,
it will become more cost effective to manufacture a single “dual-core” die,
but undoubtedly there will always be new functionality and performance,
which could be added by making use of MCM packages.

Example Assembly Flow

The final steps to create a working microprocessor combine the silicon
die with its package. The previous chapter described the steps to process
a CMOS wafer. We are now ready to complete our example processor
product by combining the die with the processor package. The common
steps for assembling a flip-chip package are:
1. Bumping
2. Die separation
3. Die attach
4. Underfill
5. Lid attach

The first step in preparing die for a flip-chip package is bumping, the
creation of solder balls that will provide electrical connections between