Page 359 - A Practical Guide from Design Planning to Manufacturing

Microprocessor Packaging 329

based on the package alone. It is common for identical die to be placed
into multiple different packages and sold as different products. For a
desktop package, balancing cost and performance might be the highest
priority. For a server product that will be sold at a very high price, a more
expensive package allowing for more performance may be justified. For
mobile products, the size of the package and enabling of dense placement
of components on the PCB is critical.
Recent packaging trends have focused on reducing the overall size of the
package to allow for smaller, more portable electronics. Any package with
an area less than 1.5 times that of the die is called a chip scale package
(CSP). These packages are created by the same methods as larger pack-
ages but use smaller lead pitches and smaller wire traces to minimize their
size. One possible approach for reducing package size still further is embed-
ding the die inside the package substrate. A bumpless buildup layer
(BBUL) package replaces a FR4 core layer with the die itself. The die does
not need C4 bumps to contact the package substrate because buildup
layers of interconnect are formed around the die. This approach has the
disadvantage that the substrate can not be manufactured in parallel with
the die, but brings packaging size down to a bare minimum.
As processors continue to increase in performance and power while
being used in an increasing variety of products, packaging will continue
to be a key part of microprocessor design.

Key Concepts and Terms
Blind and buried vias Multichip module (MCM)
C4 bump Printed circuit board (PCB)
Coefficient of thermal expansion (CTE) Socket
DIP, quad package, grid array package Surface mount technology (SMT)
Direct chip attach (DCA) Through hole technology (THT)
FR4 and alumina Under-bump metallization (UBM)
Integrated heat spreader (IHS) Underfill
Known good die (KGD) Wire bond and flip-chip
Microvia

Review Questions
1. What are the main design choices when choosing a package?
2. Compare modeled plastic, ceramic laminate, and organic laminate
packages.
3. Why are the CTE of package materials important?
4. What does Rent’s rule predict for the scaling of microprocessor lead
counts?