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Source: SEMICONDUCTOR MANUFACTURING HANDBOOK

CHAPTER 16

ECD FUNDAMENTALS

Tom Ritzdorf
John Klocke
Semitool, Inc.
Kalispell, Montana

16.1 INTRODUCTION

In the early years of semiconductor processing, transistor gate delays determined chip speed. However,
as devices shrank, the RC delay in the metallization (interconnect) levels became an important
factor determining the chip speed. Copper, which has the second lowest resistivity of all metals, has now
replaced aluminum in interconnect metallization for high-performance chips because of its low
resistivity and improved electromigration lifetime. This required significant changes in the fabrication
process such as switching to a damascene process flow and implementing electrolytic copper deposition
and copper chemical mechanical polishing (CMP) in the semiconductor industry. Although electroplat-
ing had been used in the manufacturing of printed circuit boards for many years, it was a new process
for chip manufacturing. This new application has spawned a wealth of research and development. The
“art” of electroplating has now been refined to a fully characterized scientific process. Additionally, other
electrochemical processes are now being considered as potential production solutions.

16.1.1 Basic Process Flow for Copper Damascene Processing

Traditional aluminum interconnects were formed through a subtractive metallization process, with
dry etching used to pattern blanket films of aluminum alloys. However, in dry etching, copper isn’t
feasible because the temperature required to volatilize copper compounds is too high to be com-
patible with semiconductor processing, so a new metallization scheme (damascene process) has
been implemented. 1–3 In damascene processing, a dielectric material is deposited and patterned
first and then metal is filled into the features. Finally, the excess material is removed, leaving an
embedded metal line or via. In dual damascene processing, a lower via level and upper metal line
layer are patterned in the dielectric material prior to metallization. Both layers can then be filled
in a single metallization process, which reduces the overall number of process steps and manu-
facturing costs.
The standard process flow for damascene copper metallization is shown in Fig. 16.1. After the
dielectric layer has been patterned, barrier and seed layers are deposited using a physical vapor depo-
sition (PVD) process. Typically the barrier layer is either Ta or a TaNx/Ta bilayer and the seed layer is
pure copper. Electrochemical deposition (ECD) is then used to fill the features with copper. The wafers
are annealed to stabilize the film and finally, the excess copper is removed with CMP.

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