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INSPECTION, MEASUREMENT, AND TEST

19.24 FINAL MANUFACTURING

There are many other tests that can be done on Flash memory devices. They include the program/
erase suspend to see if the program or erase steps can be suspended and resumed, testing block lock-
ing that checks the ability to prevent overwriting certain data when the part is locked, and other data
security feature functions. These tests are usually specific to the feature set of the Flash memory
device.

Typical Production Test Flows. Sort 1 is the first time a Flash (memory) device is checked on a
wafer after the IC fabrication steps. This is where the DUT’s voltage reference cells are trimmed.
This allows the DUT to determine the difference between a logic “0” and a “1” state. After setting
up these thresholds, the DUT is checked for basic program and erase functionality as well as check-
ing for slow or fast programming bits. Any FETs that do not stay within predetermined limits for Vt
and other characteristics are marked for potential repair with redundant elements. Other tests may or
may not be done depending on the feature set. High fallout tests are done at Sort 1 to weed out the
bad DUTs early. Devices that pass Sort 1 are programmed with a pattern and sent to the burn-in
ovens shown in Fig. 19.1; this step is called the retention bake. Since the oxide layers are so thin,
any anomalies that prevent the proper storage of the charge on the floating gates are judged defec-
tive. The retention bake step is a form of accelerated aging to determine if the DUT will be able to
retain data for its specified lifespan.
Sort 2 is a wafer level test that quantifies the amount of charge loss or gain to see if it falls within
the allowed limits. Retrimming of the reference cells is done and the Vt distributions are again
checked with margin tests. Any bits that do not pass this step are repaired with redundant elements.
A custom pattern is then programmed into the part, and it is sent to packaging.
Sort 3 or package test runs a simple functional test to make sure that the packaging step did not
damage the DUT. For KGD sales, the package step is not done, but the equivalent is done on the
wafer prior to die separation. The last step is to program any of the custom features of the DUT and
program any data desired by the end customer.

What Makes Testing Flash Memory Difficult? Flash memory testing is difficult because the pro-
gram and erase execution times are long. In order to get the electrons onto or off of the floating gate,
the three terminals of the FET need to be held at certain voltage levels. This allows electrons to
migrate across the barrier oxide and get trapped or released. Since program/erase time and data
retention are both affected by the thickness of the barrier oxides, a tradeoff between the two charac-
teristics must be made. To achieve the goal of 20 years of data storage, the program and erase times
end up being much longer than equivalent times for SRAM or DRAM, for example, µS or mS
instead of nS. This means that total test time for Flash memory is much longer than that of other
volatile memory technologies. Testing all the characteristics of a Flash memory device can take on
the order of minutes. Because of this, Flash algorithms are designed to make the best use of several
test patterns that overlay to minimize unnecessary erases. For this reason, patterns common with
SRAM and DRAM testing such as walking 1s and 0s are not used in Flash testing.
With Flash densities ever increasing and the number of individual FETs in a device growing, the
number of memory cells is large. Densities of several gigabytes are available today, meaning that
several billion FETs per device must be checked. Combining long program and erase times with bil-
lions of FETs results in even longer test times. This is why most manufacturers resort to as much
parallelism as the latest tester and probe card technologies will allow. Higher parallelism increases
complexity since more resources must be coordinated and more data must be managed.
There is a need for redundant memory cells because with billions of FETs, it is virtually impos-
sible to guarantee that each one will be fully functional after all the complex fabrication steps. One
speck of dust can damage an entire device. For this reason, each Flash memory device is made
with redundant rows and/or columns to allow the device to be repaired during a test. This means
the redundant elements must also be checked for proper functionality and the test program must
manage the swapping and tracking of errors in the main array as well as the redundant elements.
The redundancy analysis and repair routines are arguably the most difficult portion of the test
process. Some devices even allow repairing of the repair elements, which further increases this
complexity.

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