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INSPECTION, MEASUREMENT, AND TEST

INSPECTION, MEASUREMENT, AND TEST 19.19

The compare memory is a table of what the tester expects to see from the DUT for each cycle and
the error memory logs the pins and locations that fail. These all interact so that a logic “1” drive com-
ing from the vector memory has the correct timing and level so that the DUT recognizes it as a valid
input, and the DUT can send the appropriate response that the comparator decodes to a logic “1” or
“0,” which is then compared against the compare memory to judge if it is the correct response. The
test may or may not run through the memory addresses in a linear fashion. A sequencer is a vector
address generator that will allow the memories to be accessed in structured ways like subroutines or
randomly move with jump operations. Also, the flexibility of being able to change from one format
or setting of edges to another in the next device cycle is desirable; this is called changing on-the-fly
(OTF). All these operations need to be orchestrated to put the DUT into its end application environ-
ment, and a test processor accomplishes this task on an individual pin-by-pin basis. All the func-
tionality described under pin electronics needs to be available on every pin, or per-pin to be able to
meet the flexibility and complexity demands of many different digital devices.
Scan has become popular with digital devices. Very large lengths, for example, over 100 Mbytes,
of Scan memory need to be available in the configuration to accommodate this need. Other specialty
functions such as capture memory and digital source memory will be covered in the mixed-signal
test section, and algorithmic pattern generator will be covered in the memory section.
Some other critical parts of the architecture include clocks and timing. Clocks are what drive the
DUT and it may need more than one domain. A different domain may use a frequency unrelated to
others used by the DUT, or be nonphase related. Overall timing accuracy (OTA) and edge-placement
accuracy (EPA) are widely considered to be the most important and fundamental specifications of a
digital tester. These specifications indicate how accurately an edge can be launched and measured
from the test system. Edge timing resolution is also critical to DUT performance as well as the jit-
ter, or the undesirable movement of edges from one device cycle to the next.
Other functions required in the architecture include power supplies, a higher precision dc para-
metric measurement unit to make more exacting measurements than the per-pin PMU can make, a
system controller or CPU to run the program, and a time interval analyzer that is used to making tim-
ing measurements on edges. The software environment needs to be interactive and graphical user
interface (GUI) based. Since the increasing speeds and number of pins make it difficult to move
enough air through a system to maintain the proper temperature, liquid cooling is a state-of-the-art
trend.
High-Speed Digital Testing. Advances in silicon, such as smaller gate widths and superior mate-
rials, and fabrication techniques have enabled extremely fast on-chip communication. In many cases,
the bottleneck of the ICs has become transporting data between chips and other system building
blocks. The need to create faster chip-to-chip interfacing has resulted in many different standards for
data transportation. Unlike sub-gigabit-per-second (Gbit/s) testing, high-speed testing involves no
tristating—as mentioned in an earlier section—because tristating causes additional capacitance.
Termination is always used to avoid reflections, and the data bus effectively becomes a high-speed
transmission line.
Understanding the particular high-speed device and its challenges is an important first step to out-
lining a test plan and determining the fit to a particular piece of ATE. For example, some standards
utilize embedded clocks, whereas others, such as HyperTransport, provide a clock synchronized with
the data and the internal phase locked loop (PLL). The latter may require an interface with source-
synchronous capabilities, whereas the former may require a clock-recovery circuit. Many cases exist
where the digital tester is asked to synchronize to a bit stream that is not deterministic or contains
seemingly random data packets.
Many high-speed bus protocols are differential based. Differential swings are typically extremely
small and require a digital tester with the ability to provide a linear signal with a well-defined, con-
trolled slew rate at low swings.
Some applications require a dual-transmission line implementation to enable fast write-to-read
transitions or to enable dedicated drive-only or receive-only ATE to interface with a bidirectional
device interface. An example is double data rate (DDR) devices that must use a driver and a receiver
to interface bidirectional DDR data pins (single ended) with ATE.

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