Page 289 - Semiconductor Manufacturing Handbook

Geng(SMH)_CH19.qxd 04/04/2005 20:00 Page 19.16

INSPECTION, MEASUREMENT, AND TEST

19.16 FINAL MANUFACTURING

designers develop so many different ASICs. Lastly, programmable logic gives the end user flexibil-
ity to make changes in what the device does to meet its end application needs.

Definition of a Digital Device. Digital data has two states—on/off, high/low, or logic “1” or “0.”
A stimulus on one or more of the inputs to the device causes a result on one or more of the outputs
of the device. It is made of transistors, or more specifically field effect transistors (FETs), configured
together to build gates. A gate is the simplest of all digital building blocks. Gates include AND, OR,
XOR, and NOT among others and can be combined to build logic for specific functions or blocks.
A device may have several blocks that, together, form a digital device. These individual bits of data
can be combined to form a byte or a word of digital data, and one bit has two possible states (0, 1).
Binary words on a digital device are also called a bus. They can be used to address memory, as the
data that go into some memory location, or as control lines.
Many companies sell digital building blocks as their intellectual property (IP). This gives the
designer access to the highest performance design and allows a designer to build a device using pro-
prietary digital blocks along with a microprocessor block from one company and an interface block
from another company to create a new device that fills a specific need.
Digital signals are received or transmitted to a device based on the device clock. The rising or
falling edge or both edges of a clock signal are used to latch data into flip-flops in the device. The
faster the clock can run, the faster the device can use data, and the faster the device can complete a
given task. Processors and ASICs may have several clocks. The device may be able to do computa-
tions internally with a clock of one frequency, yet transmit and receive data at much different speeds.
In this case, the device may generate its own clock, using a phase-lock loop, and transmit data to
other devices according to that clock. The highest clock frequencies are generally used inside a
device to do computations; other clock speeds are used to reduce the risk of bit errors in communi-
cating to other components.

Functional, Structural, and Defect-Based Tests. A common way to test a digital device is by
using functional tests that exercise the digital inputs the same way as they would be used in the end
application. For instance, with an “AND” gate, the following sequence of inputs—00, 01, 10, 11—
would produce these outputs—0, 0, 0, 1. IC designers simulate device operation to make sure their
design is correct. Test vectors are then generated from this simulation data. As the number of gates
on a digital device grows, the time it takes to simulate the device and the number of vectors required
to test it grow exponentially. Devices with millions of transistors cannot feasibly be simulated com-
pletely because of time-to-market (TTM) pressures and the costs of added simulation and test equipment
(such as larger memory and more processing power required). Therefore, engineers can design test
circuitry into the device and use a combination of functional and structural tests to verify the device’s
operation. Simple functional tests are written to test the interconnects between different blocks with-
in a device and structural tests are written to test the individual gates.
A design-for-testability review can determine which of these methods are needed for a partic-
ular device. Structural tests seek to verify that all the pieces of the product circuit are present and
working. Alternatively, a structural test verifies that the DUT is free of faults but does not attempt
to verify that it performs to all its specifications. The most common digital structural test is scan.
With scan tests, the designer must use scan flip-flops and when the chip is placed in scan mode,
special input pins on the device can shift data serially through chains of these registers and into
particular flip-flops. Data that are required to test for a specific fault can be easily applied to the
gate inputs. After the correct data are placed in the flip-flops, the device is clocked once and data
are captured by scan flip-flops at the output of these gates. That data are shifted out serially and
compared against the data predicted by simulation. Multiple “chains” of scan registers can be
tested in parallel for added throughput. Any data can be placed into any gate so the fault coverage
is very high. The down side is that the data for all these different serial scan chains require lots of
vector memory and, since the scan lines have typically lower speed than the rest of the device, the
test time can be long.
A third test strategy is known as defect-based testing (DBT). DBT attempts to detect defects in a
circuit by measuring any of its outputs while looking for unusual behavior, even if it is within

Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com)
Copyright © 2004 The McGraw-Hill Companies. All rights reserved.
Any use is subject to the Terms of Use as given at the website.