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INSPECTION, MEASUREMENT, AND TEST

INSPECTION, MEASUREMENT, AND TEST 19.21

More than one cell may be enabled by an address so that multiple bits of data may be manipu-
lated at the same time. For instance, a memory device with a 1 Mbit capacity has 1048576 cells in
its array. These cells may be organized as 131072 addresses that enable eight cells at a time. This
would commonly be known as a 128K × 8 memory device. Likewise, the same memory might
instead be organized as a 64K × 16 device.

Basic Memory Test Setups. Similar to other types of digital semiconductor devices, the test setup
includes pin configurations, voltage levels, timing conditions, and test patterns determined by the
design of the device. Different logic designs require different timing and level setups. For example,
a device with high speed transistor logic (HSTL) outputs would require one set of voltage and tim-
ing conditions while a device using stub series terminated logic (SSTL) 1.8 compliant off chip dri-
vers would require a completely different set of conditions. In general, there are three steps
involved in the testing process—determining the fault coverage requirement, planning and imple-
menting the test setup, and finally analyzing the test results.
A good understanding of the fabrication process, such as historical data and a good understanding
of the design determine the fault coverage requirements. This was discussed in Sec. 19.1. Early in the
design process, decisions must be made about the level of BIST. In one extreme, designers could imple-
ment BIST engines to accomplish most of the functional memory tests, leaving the standard dc para-
metric test to ATE. Or, the design might not provide enough extra space for the BIST circuitry on the
silicon die, in which case all the testing, including functional dc and ac, would be performed with ATE.
The functional testing of a memory device can be viewed as three parts—the memory core con-
sisting of memory cells, the address decoders consisting of logic used to select a particular section of
the memory array, and finally the logic used to control device operations such as read, write, and
refresh. Each section of the memory requires different patterns to test for proper functionality. Some
of the fault models are the same as any other logic device such as stuck-at faults or stuck-at logic “0”
or “1.” Because of the way a memory design is laid out, other faults also apply. These are called neigh-
borhood sensitive faults that have to do with the proximity of one element to another. Some examples
of this are coupling faults defined as cross talk between data lines or electrical shorts between data
lines, and address decoder faults defined as inaccessible address lines or multiple cell access faults.

Architecture of a Memory Tester. Stand-alone memory devices are typically tested with algorith-
mic pattern generators (APGs). An APG generates tester cycles that contain a pattern to execute a
series of write and read operations of data to a predetermined sequence of addresses. The tester will
capture results from the read operations and compare them to the expected data. There are two mem-
ory tester architectures to consider—per-pin and centralized. The centralized architecture imple-
ments the APG using hardware architected as a collection of programmable hardware registers. The
contents of the registers are gated to dedicated tester buses for address pins, data pins, and control
pins. In contrast, a tester with a per-pin architecture provides identical functionality using a software
APG that programs each tester channel to execute a memory test.
The centralized APG architecture is a traditional tester implementation that does a good job of test-
ing standard memory devices. The per-pin architecture provides a flexible memory test solution that
does not use dedicated tester buses and can generate APG patterns as well as logic patterns. This allows
the per-pin architecture to be used to test standard memory devices as well as new memory architec-
tures that also contain logic. This capability is also very useful in testing embedded memories.
Test Result Analysis. A requirement when characterizing memories is to represent the pass/fail results
in a graphical format. The graphical display, known as a bitmap display, shows a two-dimensional depic-
tion of the memory array and the passing and failing bit represented by different characters or colors.

19.2.6 Testing Flash Memory Devices
Flash Market Segments. Flash memory is a huge market and very pervasive in our day-to-day
lives. Any device that needs to remember something without power is a good candidate for Flash
memory. This includes cell phones, digital cameras, PDAs, MP3 players, computer BIOS, and memory
used as small external drives for a PC.

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