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INSPECTION, MEASUREMENT, AND TEST

19.22 FINAL MANUFACTURING

Definition of Flash Memory. Flash memory allows users to electrically program and erase infor-
mation and is a nonvolatile memory; that is, power can be removed from the circuit, and it will retain
the information. Flash memory is similar to erasable programmable read-only memory (EPROM),
but with a much thinner oxide layer between the gate and the source/drain. Each individual Flash
memory cell is a FET with a modified gate structure. The gate structure has a floating gate where
electrons are trapped or stored. By trapping or storing these electrons, the threshold voltage of the
FET is raised and it is considered programmed. When the electrons are removed from the floating
gate of the FET, it is considered erased.
The process of storing and removing charge is complicated. It requires that certain voltages be
placed on the contacts of the FET for controlled periods of time. It is possible to over-program or
over-erase the FETs causing the memory device to cease functioning. Users typically want to deal
with bytes or words instead of individual bits. Because of this, the Flash memory device contains a
state machine that is a microcontroller that acts as a user interface. The user issues predetermined
commands to the Flash memory device, such as “program this word,” or erases some portion of the
Flash memory, and the microcontroller does the low-level work of moving the charge onto or off the
floating gate of each affected FET.
Different Flash memory manufacturers have various features and gate structures that enhance this
basic behavior. One approach is to store different levels of charge to allow multiple bits of informa-
tion per cell. Another is to modify the FET structure by allowing the floating gate to store different
charges at each end of the gate thus allowing multiple bits per FET. In any case, the trend is to store
more bits in less space thus reducing the cost per bit.
There are two different types of Flash memory technologies—NOR and NAND.
NOR: The data words can be accessed in any order (random access). This type of Flash memory
is typically used for code or code and data storage. Codes can be executed directly from the Flash
memory because the random access allows looping and branching to different locations in the
device. Typical end applications are for cell phones, PDAs (internal storage—not the Flash memory
storage cards), and PC BIOS.
NAND: The data words are accessed a page at a time, with the data clocked out of a buffer. This
type of Flash memory is typically used for data storage. Since the access is somewhat serial, the data
are usually buffered to some other memory (SRAM/DRAM) if the code is to be accessed. Digital
cameras and MP3 players typically use this type of memory since the data access is usually in order.
This is the memory in all the Flash memory storage cards—Compact Flash (CF), SmartMedia,
Secure Digital (SD), eXtreme Digital (XD), and memory stick.

Architecture of Flash Memory Tester. The typical Flash memory tester architecture is shown in
Fig. 19.8 and will be described in this section.
Since Flash memory consists of millions of similar FETs that require a similar algorithm to test,
the APG allows the manufacturer to create an algorithm for one FET and then simply set up ranges
for the amount of rows, columns, and blocks (X, Y, and Z address generators) to test.
Crossover or scrambling circuitry is needed to map the address generators to the correct address
pins since Flash memory devices have different numbers of rows, columns and blocks, circuitry.
Parametric measurement units (PMUs) are used to measure voltage or current parameters on each
FET. This architecture also allows “trimming” the device, where the reference cells and comparators
are programmed to differentiate between a logic “1” and a “0” state. Since there are so many FETs
and either 8-, 16-, or 32-bit wide data buses, multiple PMUs, or even per-pin measurement units
(PPMUs) are configured into the architecture to speed the testing.
Parallelism. Testing a Flash memory device takes a large amount of time because of the relatively
low speed and large size. To reduce cost, Flash memory manufacturers typically test multiple devices at
the same time. This requires that the resources to test each device be duplicated and that the system must
support multiple APGs and have enough pins for all the address, data, and control pins of the DUTs.
The individual test site controller is where the test program runs. It is responsible for quickly con-
trolling the APG and the other test resources. It saves the data and is also responsible for displaying
the test results.

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