Page 290 - Semiconductor Manufacturing Handbook
P. 290

Geng(SMH)_CH19.qxd  04/04/2005  20:00  Page 19.17




                                                INSPECTION, MEASUREMENT, AND TEST

                                                                        INSPECTION, MEASUREMENT, AND TEST  19.17

                                  specification. The most widely used class of DBT methods is based on measuring the circuit’s qui-
                                  escent power supply current. Called I  , these methods are most useful in complementary metal
                                                              DDQ
                                  oxide semiconductor (CMOS) circuits. Ideally, in a CMOS device no current should flow from the
                                  supply when the device is powered on but not running. Any current that flows is the result of leaky
                                  FETs or defects, usually bridges between interconnect lines that bias gates of the series connected
                                  n-channel MOS (NMOS) and p-channel MOS (PMOS) FETs away from the supply rails such that
                                  both FETs are weakly turned on and current can flow from V  to Gnd. Once a device is character-
                                                                              DD
                                  ized to have a certain I  value, any part with I  above that can be considered a bad part. The
                                                   DDQ                DDQ
                                  device is usually put into its quiescent state(s) by scanning in patterns so I  tests are built on top
                                                                                        DDQ
                                  of structural scan tests.
                                    As FETs get smaller, their natural leakage increases rapidly, which makes it harder to distinguish
                                  the defect current from the defect-free current. More advanced I  tests have been developed for
                                                                                 DDQ
                                  small geometry devices including Delta I  and I  current signatures. These tests make multiple
                                                                DDQ   DDQ
                                  I   measurements with the device programmed to be in various “quiet” states. Extreme changes
                                   DDQ
                                  indicate a failure. These more advanced methods require considerable characterization.
                                    A common alternative to the accessibility, resources, and time required to read patterns into a
                                  device from an external tester is built-in self-test (BIST) that can execute either functional or struc-
                                  tural tests. A very high-speed or very dense digital block may not be able to be tested with scan. BIST
                                  is implemented as a small state-machine circuit built into the device itself. This circuit generates
                                  inputs and compares outputs of a particular block in a device. Programming the device to drive ran-
                                  dom data can test a high-speed circuit using the device’s own input pin to receive that data and com-
                                  pare it to an expected result. BIST can be implemented as part of the device or off the device
                                  employing so-called built-out self-test (BOST) as a small circuit on the wafer that is physically cut
                                  off when the device is packaged.
                                  Deterministic Versus Nondeterministic Behavior.  Traditional functional testing has been done
                                  using deterministic patterns that can be defined prior to testing. These patterns typically came from
                                  simulations of the device and contain stimulus and response data. The stimulus signals are intended
                                  to exercise the DUT and the response signals are the results of the simulations based on the stimu-
                                  lus. The part being tested is exercised to validate that it matches the simulated responses; for a given
                                  input there is only one correct output.
                                    Nondeterministic behavior has multiple forms, but the basic definition is that an algorithm or pro-
                                  tocol has to be used to determine the correctness of the outputs and cannot be predicted prior to exe-
                                  cution, thus there can be no previously generated “expect data.” This can take the form of either the
                                  data or the execution timing being the variable.
                                    For data, this means with a given input, there is a range of valid outputs for a good device. For
                                  timing, this means that timing of the comparator strobe is set by finding the timing placement of
                                  some pin and measuring additional pins relative to this timing location.

                                  Basic Setup for Digital Test.  The basics of setting up and running a digital test include defining
                                  the pin configuration, or DUT pin to tester resource mapping, the voltage levels, the timing of the
                                  pin edges, and bringing the definitions of the correct drive and receive states, or vectors into a frame-
                                  work to develop a program. Most of this data can be leveraged from EDA. The dc tests are explained
                                  in the common test section.
                                    Additional ac tests include functional tests where vector inputs are given and outputs compared
                                  to, timing tests to find out where the edges produce a passing result and where they do not, level tests
                                  to dynamically find input and output sensitivity, propagation delay that determines the amount of
                                  time taken to get through a circuit, and setup and hold measurements that determine how long an
                                  input needs to be set up before a clock and how long it needs to be held after a clock cycle occurs.
                                  Other tests include frequency measurements, jitter measurements, and sweep tests. A sweep test
                                  moves either a voltage, timing edge, or frequency through a range of values, and then determines
                                  where the device passed and where it failed. Usually this is a characterization test since it is time
                                  consuming. Often in production a single test functional pattern will be run with critical timing and/or
                                  levels and a pass or fail status is determined.



                             Downloaded from Digital Engineering Library @ McGraw-Hill (www.digitalengineeringlibrary.com)
                                        Copyright © 2004 The McGraw-Hill Companies. All rights reserved.
                                          Any use is subject to the Terms of Use as given at the website.
   285   286   287   288   289   290   291   292   293   294   295