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INSPECTION, MEASUREMENT, AND TEST

19.20 FINAL MANUFACTURING

Setup and hold and skew measurements are typically important in the world of high-speed tests
and the ATE hardware must be able to accurately measure skews and setup and hold times.
One of the most important high-speed parameters is jitter. The impact jitter has, as it is introduced
to a device, is to cause a connected receiver to detect an incorrect bit transition, causing a fault.
Generally, the tester needs to be able to inject and measure jitter. A jitter tolerance measurement
requires that the tester inject a known amount of jitter while the device’s outputs are monitored for
an effect on the bit error rate as a functional test. Jitter transfer, on the other hand, is a measure of
how a device amplifies or transfers jittery input to its outputs. The ability of the device’s PLL to fil-
ter out the jitter is of key importance. For this test, the tester provides a jittery source and the device’s
transfer of the jitter is characterized.
Eye diagrams are another commonly used, graphical way to view the total jitter present on a device,
as measured by the test system. An eye diagram is a composite view of all the bit periods of a captured
waveform superimposed on each other. To create an eye diagram with a digital tester, the pattern is typ-
ically executed multiple times; each time the edge position and/or strobe levels are modified. The hor-
izontal size and overall shape of the eye indicates the jitter present on the device. The shapes of the eye
crossings indicate whether or not deterministic jitter is present in addition to random jitter.
Devices with source-synchronous outputs can require a different approach to tests than traditional
techniques. The main difference in testing these outputs is the nondeterministic placements of the
transitions of output signals. Traditional devices have specifications that define the timing relation-
ship of the inputs to the outputs. Source synchronous devices do not have such a specification;
instead, the data output is also accompanied with a clock signal that is coupled to the data. For
ATE, this means that the output clock of the device has to be used to sample the data. Today, many
of the source synchronous parts can tolerate huge shifts in output placement, two to four data bit
times in the system, and are able to be tested without the use of source synchronous capability. In
this case, searching for the best place to capture the data is one way of using testers without
source-synchronous capability.

19.2.5 Testing Memory Devices

Market Segments. Memory densities and speeds are continually driven by market demands. Memory
is prevalent in almost all applications that use semiconductors. Typical memory markets include per-
sonal computers, workstations, game consoles, personal digital assistants (PDAs), and mobile phones.

Architecture of a Memory Device. Semiconductor memories can be categorized into two general
types—volatile and nonvolatile. A volatile memory loses its data contents when its power is switched
off while a nonvolatile memory retains its data without power. The most common nonvolatile mem-
ory is also known as Flash memory and is discussed in Sec. 10.2.6. Volatile memory cells can be fur-
ther classified as SRAM or dynamic random access memory (DRAM). To retain data, a DRAM cell
requires a data refresh operation at regular intervals and if power is removed, all data are lost. An
SRAM cell will retain data as long as a power source is applied. The reason for this behavior, in both
cases, can be found in the design.
In order to maximize memory density, high-density DRAM memory arrays are designed with a
single transistor with a capacitor load to hold the data. The charge stored in a DRAM cell would
eventually leak off if not for the refresh operation. A refresh reads the current data and writes it back
to the DRAM which renews the stored charge in the DRAM cell, hence, the term dynamic memory.
An SRAM cell is implemented with multiple transistors to latch the data and eliminates the need for
a refresh operation.
Semiconductor memories are typically organized as an array of cells, each one containing a logic
bit “1” or “0,” of information. These arrays are typically very regular. The dimensions of the array
are denoted by X and Y, or rows and columns. Through row and column select lines; each cell may
be individually enabled for reading and writing. The X dimension address corresponds to the row
enables and the Y dimension address to the column enables, although for some manufacturers these
X and Y definitions are reversed. An address is placed on the address pins of the device, which is
then internally decoded to enable the required cells.

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