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COPPER, LOW-k DIELECTRICS, AND THEIR RELIABILITY

4.12 SEMICONDUCTOR FUNDAMENTALS AND BASIC MATERIALS

evaluates the effect of package on the reliability of the chip. The objective is to determine whether a
particular packaging scheme has any adverse effect on the chip’s functionality. Several kinds of
structures are monitored while modules (chips with their packages) are subjected to stress. JEDEC
defines a set of standardized tests to determine this reliability for different kinds of packages like
organic, C4, and ceramic. Test structures on the chip are monitored for resistance shifts and leakages.
The stresses are similar to those done at the chip level. High-temperature storage, hermiticity of the
package under temperature, humidity, bias, and thermal cycling are kinds of stresses done to evalu-
33
ate the reliability. Landers et al. have discussed the CPI results of the 90-nm CVD low-k SiCOH
technology.
The introduction of copper and low-k dielectrics has been an incredible challenge to the semi-
conductor industry. New materials and integration schemes had to be devised to implement this novel
technology. And with the industry trying to keep up with Moore’s law, more collaboration among
design, development, and manufacturing teams is the need of the hour.

REFERENCES

1. D. Edelstein et al., “Full-Copper Wiring in Sub-0.25 um CMOS ULSI Technology,” Proceedings of the IEEE
International Electron Devices Meeting, pp. 773–776, IEEE, Piscataway, NJ, 1997.
2. C. K. Hu et al., “Copper Interconnections and Reliability,” Mater. Chem. Phys., Vol. 52, p. 5, 1998.
3. C. W. Kaanta et al., “Dual damascene: A ULSI wiring technology,” Proceedings of 8th International IEEE
VLSI Multilevel Interconnection Conference, pp. 144–152, IEEE, New York, 1991.
4. J. M. Harris et al., “Studies on the Al O –Ti–Mo–Au metallization system,” J. Vac. Sci. Technol., Vol. 12,
2 3
No. 1, pp. 524–527, 1975.
5. J. D. McBrayer et al., “Diffusion of metals in silicon dioxide,” J. Electrocem. Soc., Vol. 133, No. 6, pp. 1242–
1246, June 1986.
6. J. Cho, “Process Integration Issues of Copper Interconnections for ULSI,” Doctoral Dissertation, Stanford
University, 1994.
7. B. Arcot et al., “Interactions of copper with interlayer dielectrics and adhesion promoters/diffusion barriers,”
MRS Proc., Vol. 203, p. 27, 1991.
8. M. A. Nicolet, “Diffusion barriers in thin films,” Thin Solid Films, Vol. 52, No. 3, pp. 415–443, August 1978.
9. D. Edelstein et al., “An optimal liner of copper damascene interconnects,” Proceedings of the Advanced
Metallization Conference 2001,” Materials Research Society, pp. 541–547, October 2001.
10. H. Rathore et al., “Reliability of copper metallization for CMOS ULSI technologies,” Interconnect and
Contact Metallization for ULSI, Proceedings of the International Symposium (Electrochemical Society
Proceedings Vol. 99–131), pp. 190–197, Electrochemical Society, Pennington, NJ, 2000.
11. K. Higashi et al., “Highly reliable PVD/ALD/PVD stacked barrier metal structure for 45 nm-node copper dual-
damascene interconnects,” Proceedings of the 2004 International Interconnect Technology Conference, pp. 6–8,
IEEE, Piscataway, NJ, 2004.
12. J. W. Hong et al., “Characteristics of PAALD-TaN thin films derived from TAIMATA precursor for copper
metallization,” Proceedings of the 2004 International Interconnect Technology Conference, pp. 9–11, IEEE,
Piscataway, NJ, 2004.
13. M. Lane et al., “Liner materials for direct electrodeposition of copper,” Appl. Phys. Lett., Vol. 83, No. 12,
pp. 2330–2332, September 2003.
14. M. Tsujimura et al., “General principle of planarization governing CMP, ECP, ECMP & CE—low down
force planarization technologies,” 2004 Proceedings of VLSI Multilevel Interconnection Conference, Institute
for Microelectronics Interconnections, p. 267. See also www.imic.org, Institute for Microelectronics
Interconnections on Chip.
15. E. Barth et al., “Integration of copper and fluorosilicate glass for 0.18 mu m interconnections,” Proceedings
of the 2000 International Interconnect Technology Conference, pp. 219–221, IEEE, Piscatawy, NJ, 2000.
16. J. Noguchi et al., “Impact of low-κ dielectrics and barrier metals on TDDB lifetime of Cu interconnects,”
International Reliability Physics Symposium Proceedings, p. 355, IEEE, Piscataway, NJ, 2001.

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