Page 317 - DSP Integrated Circuits
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302 Chapter 7 DSP System Design
Figure 7.21 Resource minimal schedule
implementation with a bit-parallel input and output format can be implemented
using shift registers as serial-parallel converters.
Figure 7.22 shows more explicitly the logic realization based on single-phase
logic [26]. The estimated device count is 2400 for the filter with an additional 400
transistors required for the control circuitry. The control unit is implemented
using a 15-bit shift register. About 2800 transistors are required for the complete
filter. The power consumption is estimated to be 0.8 nJ/sample. A sample fre-
quency of 35 MHz corresponds to a clock frequency of 105 MHz and 30 mW. The