Page 319 - DSP Integrated Circuits
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304 Chapter 7 DSP System Design
Figure 7.23 Maximally fast, resource minimal schedule
It is interesting to compare this implementation with the bit-parallel
implementation that used one clock cycle (35 MHz two-phase clock) per sample and
had seven bit-parallel carry-save adders. The bit-parallel implementation requires
77 full-adders while the bit-serial requires only 36 full-adders and uses only 2.5
