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358                                              Chapter 8 DSP Architectures


            We will discuss different types of interconnection networks in more detail in
        section 8.6.1.
            The difference between system
        and subsystem architectures is
        essentially due to the difference in
        granularity of the processes exe-          Figure 8.2 Cascade form
        cuted. Process granularity tends to
        be larger at the higher levels and
        lower at tne subsystem levels. For example, a process at tne system level may be
        an FFT and at the lowest level an arithmetic operation. In practice, the most com-
        mon architectures at the higher system levels are the cascade form and the paral-
        lel form, shown in Figures 8.2 and 8.3, respectively.
            Other common system architectures have
        feedback loops and may have several levels of
        hierarchies. Large DSP systems are usually
        organized as hybrids of these forms. From a
        computational point of view, the cascade form
        is well suited for pipelining while the sub-
        systems can be executed concurrently in paral-
        lel form.
            Most decomposition approaches at the
                                                        Figure 8.3 Parallel form
        higher system levels exploit the fact that many
        DSP algorithms are naturally partitioned into
        parts with small intercommunication require-
        ments. The first design step is therefore to identify these parts. Internally these
        parts may have high communication demands, for example, a recursive digital fil-
        ter. Such tightly coupled parts of an algorithm must be implemented using shared-
        memory architectures. These architectures will be discussed in section 8.9.
            A   message-based    system
        architecture, with the subsystems
        as components, can be chosen if
        the communication requirements
        between the subsystems are
        small. Otherwise, the system
        must be implemented with a
        shared-memory architecture. Mes-
        sage-based architectures will be
        discussed in section 8.6.
            The subsystems can be imple-
        mented using, for example, a stan-
        dard digital signal processor
        (uniprocessor architecture) or an
        ASIC processor if the work load is
        small, whereas a specialized multi-
        processor architecture is required
        for larger work loads. A complex
        DSP system can be composed of
        several architectural alternatives  Figure 8.4 DSP system implemented using
        as illustrated in Figure 8.4.                several types of architectures
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