Page 531 - DSP Integrated Circuits

516 Chapter 11 Processing Elements

Figure 11.51 Half of a complex multiplier using TSPC (true single-phase clocking)

at 5 V and 400 MHz. Also in this case the power consumption due to the clocking
and control circuitry is much larger than the power consumption in the logic cir-
cuitry. However, the clock load can be reduced significantly by using D flip-flops
with fewer clocked transistors. The energy consumed per complex multiplication
(16-bit sample and 8-bit coefficient) is

Hence, the higher speed of this multiplier compared to the one realized with
two-phase logic is obtained at the expense of increased chip area and, more impor-
tantly, much higher power consumption per sample. It is therefore too early in the
design process to determine the number of processing elements and the required
clock frequency. It may often, from a power consumption point of view, be efficient
to increase the number of processing elements and thereby allow the use of a more
power-effective but slower logic style. Further, any excess speed may be converted
to a reduction in the power consumption by reducing the power supply voltage
until the speed is just adequate.

11.19 FFT PROCESSOR, Cont.

The decimation-in-frequency radix-2 bit-serial butterfly PE has been implemented
in a 0.8-um standard CMOS process. The PE has a built-in coefficient generator
that can generate all twiddle factors in the range 0 to 128, which is sufficient for a
1024-point FFT. The butterfly PE can be implemented using the complex multi-
plier and the two complex adders (subtracters), as shown in Figure 11.52.
A complex adder requires only two real adders while the multiplier requires
two distributed arithmetic units. The maximum clock frequency at 3 V supply volt-
age is 133 MHz with a power consumption of 30 mW (excluding the power con-
sumed by the clock). In order to estimate the power consumption in the different
parts of the butterfly, simulations were made in Lsim Power Analyst™. The simu-