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6.10 INTRODUCTION TO VHDL DESCRIPTION OF COMBINATIONAL PRIMITIVES 283

rr~v im3
3 b— —
a b a_gt_b a_eq_b a_lt_b a(H)-t — 1
on . u b(H)-t— — T)>^i
0 0 gt eq It L_J\oim2 — ^ a_gt_b(H)
01 0 0 1 ^2
10 1 0 0 _ A im5
5 b— —
1 1 gt eq It V*
(a) f TV^
' J
gt(H) 8 V^.
— a i___y
b a_gt_b eq(H) 1—vyn±
-j
1-Bit b
a
e
- gt Comparator — "—
I lt(H) n V=?- a_lt_b(H)
eq a_lt_b X
It f .^A im10
12 b— —
(b) (c)
FIGURE 6.43
Design of the cascadable bit-comparator, (a) Truth table, (b) Logic circuit symbol, (c) Circuit diagram
in NAND/INV logic according to Eqs. (6.25).

propagation delay, denoted as avgjdelay, is computed in each gate model at the end of the
VHDL description by using (tplh+tphl)/2, which is Eq. (6.1) discussed in Subsection 6.1.3.
The propagation delays are defined in Fig. 6.2. As in the two previous examples, the VHDL
keywords and logic operators are indicated in bold for visual effect. Two new keywords have
been added: generic map associates constants within a portion of the VHDL description
to constants defined outside that portion; port map associates port signals within a portion
of the VHDL description to ports outside of that portion.
The following is the complete gate-level VHDL description of the 1-bit comparator given
the name bit-compare:

entity bit_compare is
generic (tplhl, tphll, tplh2, tph!2, tplh3, tph!3: time);
port (a, b, gt, eq, It: in bit; a_gt_b, a_eq_b, a_lt_b: out bit);
end bit-compare;
architecture behave_comp of bit-compare is
begin
a_gt_b <= T when a > b else '0';
a_lt_b <= T when a < b else '0';
a_eq_b <= gt if gt <= T else
eqif eq <= T else
It if It <='!';
end behave _comp;