Page 308 - Engineering Digital Design

6.10 INTRODUCTION TO VHDL DESCRIPTION OF COMBINATIONAL PRIMITIVES 279

a considerable savings in transistor count and design area, as indicated in Fig. 6.39b. Here,
the MUX is enabled and buffered by using a tri-state driver with an active low control input.
Thus, the disable condition [EN(L') = 0(L)] is actually a disconnect state as indicated in
Fig. 3.8b and is represented by the dash in the truth table of Fig. 6.39a. Notice that the AND
plane, equivalent to the four four-input NAND gates in Fig. 6.4d, is constructed with only
eight transmission gates, and that the OR operation is "wired" to the tri-state driver since
only one line can be active at any given time. Consequently, the transmission gate design
represents a significant savings in hardware cost and will be faster (shorter throughput)
compared to the NAND gate design in Fig. 6.4d.
An important aspect of steering logic designs is that the transmission gates are non-
restoring devices and must be buffered to prevent degradation of the signal. The following
is offered as a "rule of thumb" in dealing with transmission gate designs:

For signal-restoring purposes in logic designs that use transmission gates, plan to
buffer each signal for every four transmission gates through which the signal must
pass. CMOS transmission gates should be counted as two pass transistors.

The design of a 2-to-4 decoder is used here as another simple example of a CMOS
transmission gate (TG) implementation of a combinational logic device. Shown in Fig. 6.40a
is the truth table for this decoder and in Fig. 6.40b is the TG implementation of the decoder
taken directly from the truth table. The outputs are shown enabled and buffered with inverting
tri-state drivers having an active low control input as in Fig. 3.8d. If active high outputs are
required, noninverting tri-state drivers of the type shown in Fig. 3.8b can be used. Notice
that each "1" CMOS TG leading to a Y output must have a "0" TG associated with it and
that all TGs have complementary EN inputs connected to them from an inverter. Thus, since
there is a series of two "1" TGs per Y output, there are two "0" TGs for each output, making
a total of 16 TGs or a total of 60 transistors, including inverters and tri-state buffer/enables.
In comparison, the gatewise CMOS NAND implementation of the same decoder yields a
transistor count of only 34. Though the transistor count for the TG design is greater than
that for the gatewise implementation, the speed (throughput) should be comparable and
perhaps a little faster for the TG design.

6.10 INTRODUCTION TO VHDL DESCRIPTION
OF COMBINATIONAL PRIMITIVES

With ever-increasing complexity of digital systems, there comes a greater need for simu-
lation, modeling, testing, automated design, and documentation of these systems. The
challenge here is to make the English language readable by a computer for computer-aided
design (CAD) purposes. Hardware description languages (HDLs) satisfy these require-
ments. VHSIC (for very high speed integrated circuit) is such an HDL. It was funded by the
Department of Defense in the late 1970s and early 1980s to deal with the complex circuits of
the time. However, the capabilities of the VHSIC language soon reached their limit, giving
way to more advanced HDLs that could meet the challenges of the future. One important
language that has emerged is known as VHSIC Hardware Description Language or simply
VHDL. VHDL was first proposed in 1981 as a standard for dealing with very complex