Page 313 - Engineering Digital Design

284 CHAPTER 6 / NONARITHMETIC COMBINATIONAL LOGIC DEVICES

architecture structure_comp of bit-compare is
component inv
generic (tplh, tphl: time); port (il: in bit; ol: out bit);
end component;
component nand2
generic (tplh, tphl: time); port (il, i2: in bit; ol: out bit);
end component;
component nancB
generic (tplh, tphl: time); port (il, i2, i3: in bit; ol: out bit);
end component;
for all: inv use entity avg_delay_inv;
for all: nand2 use entity avg_delay_nand2;
for all: nand3 use entity avg_delay_nand3;
— Intermediate signals must be declared:
signal iml, im2, im3, im4, im5, im6, im7, im8, im9, imlO: bit;
begin
a_gt_b output
gatel: inv generic map (tplh, tphl) port map (a, iml);
gate2: inv generic map (tplh, tphl) port map (b, im2);
gate3: nand2 generic map (tplh, tphl) port map (gt, a, im3);
gate4: nand2 generic map (tplh, tphl) port map (gt, im2, im4);
gate5: nand2 generic map (tplh, tphl) port map (a, im2, im5);
gate6: nand3 generic map (tplh, tphl) port map (im3, im4, im5, a_gt_b);
a_eq_b output
gate?: nand3 generic map (tplh, tphl) port map (eq, iml, im2, im6);
gateS: nand3 generic map (tplh, tphl) port map (eq, a, b, im7);
gate9: nand2 generic map (tplh, tphl) port map (im6, im7, a_eq_b);
a_lt_b output
gate 10: nand2 generic map (tplh, tphl) port map (It, iml, im8);
gatel 1: nand2 generic map (tplh, tphl) port map (It, b, im9);
gate 12: nand2 generic map (tplh, tphl) port map (iml, b, imlO);
gate!3: nand3 generic map (tplh, tphl) port map (im8, im9, imlO, a_lt_b);
end structure_comp;

The following are the gate model descriptions for inv, nand2 and nand3:
entity inv is
generic (tplh: time := 4ns; tphl: time := 2 ns);
port (il: in bit; ol: out bit);
end inv;