Page 318 - Engineering Digital Design

PROBLEMS 289

6.2 The voltage parameters for a high-speed CMOS (HC) gate are measured to be V IL max =
0.23V DD and V [Hmn = G.59V DD with V OLmax = 0.08V DD and V o//min = 0.90V DD for
a supply of 2.8 V.
(a) Calculate the noise margins for this gate.
(b) Use the values calculated in part (a) to explain what they mean in relationship to
the interpretation of logic 1 and logic 0 for this gate.
6.3 Construct a logic circuit that combines two 16-to-l MUXs to form a 32-to-l MUX.
(Hint: Use an inverter to select the appropriate MUX.)
6.4 Use an 8-to-l MUX to implement each of the following functions, assuming that all
inputs and outputs are active high.
(a) W(A, B, C) = £>(!, 2, 4, 5, 6)
(b) X(A, B, C) = ABC + ABC + ABC + ABC + ABC
(c) Y(A, B, C) = H M(Q, 1,2,6, 7)
(d) Z(A, B, C) = (A + B) O (AC) + AB
6.5 Repeat Problem 6.4 but instead use a 4-to-1 MUX to implement each function. To do
this use minimum external logic and the two most significant inputs as the data select
variables.
6.6 Repeat Problem 6.5 assuming that only input B arrives from a negative logic source
and that one inverter is permitted to be used on a data select input.
6.7 Use a 4-to-l MUX to implement each of the following functions, assuming that all
inputs and outputs are active high. It is required that minimum external logic to the
MUX be used in each case, and that the data select inputs be A and B.
(a) U(A, B, C, D) = £ m(0, 4, 5, 7, 8, 9, 13, 15)
(b) V(A,B,C, D) = Y\M(0,5,S, 9, 11,12,15)
(c) W(A, B, C, D) = £>(4, 5, 7, 12, 14, 15) + 0(3, 8, 10)
(d) X(A, B, C, D) = 0 M(0, 1, 2, 5, 7, 9) • 0(4, 6, 10, 13)
6.8 Implement the following function by using the hardware indicated (nothing else).
Assume that the inputs arrive as A(H\ B(L), C(H), and D(L), and that the output is
issued active high.

F(A, B, C, D) = J^m(0, 1, 3, 4, 6, 8, 9, 10, 11, 12, 15)
Permitted hardware: One 4-to-l MUX; one NAND gate; one XOR gate.

6.9 Implement the following function by using the hardware indicated (nothing else).
Assume that the inputs arrive as A(L), B(H), C(H), and D(H), that the output is
issued active high. (Hint: First find the absolute minimum expression for Z.)
Z = ACD + ABCD + (A + B)CD + (A O B)CD

Permitted hardware: One 2-to-l MUX; one NAND gate; one AND gate.
6.10 (a) Configure a 6-to-64 decoder by using only 3-to-8 decoders.
(b) Configure a 6-to-64 decoder by using only 4-to-16 and 2-to-4 decoders.