Page 314 - Engineering Digital Design

6.10 INTRODUCTION TO VHDL DESCRIPTION OF COMBINATIONAL PRIMITIVES 285

architecture avg_delay_inv of inv is
begin
ol <= not il after (tplh + tphl)/2;
end avg_delayl;
entity nand2 is
generic (tplh: time := 6ns; tphl: time := 4 ns);
port (il, i2: in bit; ol: out bit);
end nandl;
architecture avg_delay_nand2 of nand2 is
begin
ol <= il nand i2 after (tplh + tphl)/2;
end avg_delay2;
entity nand3 is
generic (tplh: time := 7ns; tphl: time := 5 ns);
port (il, i2, i3: in bit; ol: out bit);
end nand3;

architecture avg_delay_nand3 of nand3 is
begin
ol <= not (il and i2 and i3) after (tplh + tphl)/2;
end avg_delay3;

In the preceding examples VHDL syntax has been applied sometimes without comment.
There are relatively few syntax rules that need be followed to create proper VHDL descrip-
tions of devices. The following are some of the more important examples of these syntax
rules:

• VHDL is not case sensitive. Upper- or lowercase characters can be used as
desired.
• Identifiers must begin with a letter and subsequent characters must be alphanu-
meric but may contain the underscore "_". For example, in Fig. 6.42 the identi-
fiers are mux4 and mux4-behavior.
• The semicolon ";" is used to indicate the termination of a statement. For example:
"end nand3;".
• Two dashes "--" are used to indicate the beginning of a comment. A comment
in VHDL is not read by the compiler but serves as a message or reminder to the
reader.

An interesting and useful feature of VHDL is that it supports what is called operator
overloading. This feature permits custom operations to be defined. The following example
illustrates how operator overloading can be used to define a new data type:
function "and" (l,r: std_logic_1164) return UX01 is