Page 323 - Engineering Digital Design

294 CHAPTER 6 / NONARITHMETIC COMBINATIONAL LOGIC DEVICES

implement the function. [Hint: The easiest approach is to count the number of
inputs (A, 5, C, and D) that are active for each cell of the fourth-order K-map.
Then enter the three EVs (in minimum subfunction form with the aid of a third-
order K-map) in those cells as needed to bring the count of active inputs to four
or more. If this is correctly done, 35 EPIs and no inverters will be required.]
(c) From the K-map in part (b), extract a gate-minimum expression by using XOR
patterns. If this is correctly done, the gate count will be reduced to 18 (a four-level
function) with no inverters required.
6.32 Design a 4-bit general shifter that can shift or rotate, right or left, up to three bits with
F fill. To do this, do the following:
(a) Construct the truth table for this shifter.
(b) Use the truth table of part (a) to plot the fourth-order K-map for each of the four
outputs.
(c) From the results of part (b), write the expression for each output in a form suitable
for a 4-to-l MUX implementation by taking the data select inputs as A\ and AQ.
Do not implement.

6.33 Find the gate-minimum external logic for a 4-bit shifter that will cause it to operate
according to the following table. To do this, make use of XOR patterns. Show the
resulting logic circuit required to be connected to the shifter assuming that all inputs
and outputs are active high.

Shifter input Action
Even 1 parity Shift right 1 position with 0 fill
Odd 1 parity Shift left 2 positions with 1 fill
1111 (Exception) Transfer
(Hint: It is only necessary to know the logic for F, D, A\, and AQ, which are the
outputs for the truth table. Properly done, the minimum external circuitry will consist
of three XOR gates, two NAND gates, and two inverters. Note that maxterm code
must be used to extract AQ from the K-map).
6.34 Combine two 4-to-l steering logic MUXs, shown in Fig. 6.39b, to produce an 8-to-l
line MUX. To do this you are permitted to use a single additional CMOS inverter and
a CMOS OR gate.
6.35 Write the VHDL behavioral description for the majority function F = AB + BC +
AC. To do this, use the keywords that are defined in Section 6.10.
6.36 Write the VHDL behavioral and structural descriptions for a 2-to-4 decoder with
active high outputs. To do this follow the examples in Section 6.10.
6.37 At the discretion of the instructor, write the VHDL behavioral description for any
device featured in this chapter. Note that more than one correct approach may exist
in writing the behavioral description of a given device.
6.38 At the discretion of the instructor, write the VHDL structural description of any device
for which Problem 6.37 has been assigned. Note that correct approaches often vary
in writing structural descriptions of devices.