Page 327 - Engineering Digital Design

298 CHAPTER 7 / PROGRAMMABLE LOGIC DEVICES

consisting of a nonprogrammable decoder (AND) section and NMOS programmable con-
nections (fusible links) on every memory bit location to form the programmable OR section.
Also shown are inverting tri-state drivers (see Fig. 3.8d) on the PROM outputs to provide
an active low enable control capability. The PROM chip is produced with all transistors
"connected" such that each memory bit position is normally active high. Thus, when a
decoder output line becomes active, all connected NMOS are turned ON, pulling those
bit positions to 0(H), resulting in a 1(H) from each tri-state driver. A bit position is pro-
grammed when a fusible link is "blown," disconnecting that bit position. Disconnected
bit positions cannot be pulled low and therefore, must remain at 1(H). If all bit positions
on an OR column are disconnected by programming, the output is 0(H) from the tri-state
driver. Or, if one or more OR column bit positions are left connected, the output will be
a 1(H) if a decoder line to one of those bit positions becomes active — the OR function.
The PROM of Fig. 7.2 is programmed (one time only permitted) with a PROM program-
mer by applying voltage pulses to target fusible links, causing disconnection of these bit
positions.
The masking process of a mask-programmable ROM places NMOS connections at pre-
determined (programmed) memory bit positions. The positioned NMOS connections would
look similar to those in Fig. 7.2, except their fusible links would be missing. Because the
masking process is expensive, mask-programmable ROMs are used only for high-volume
commercial applications.
Much more useful, generally, are the EPROMs, since they can be programmed, erased,
and reprogrammed many times. These devices fall into two main categories: ultraviolet
erasable PROMs (UVEPROMs) and electrically erasable PROMs (EEPROMs). In either
case the technology is similar — use is made of floating-gate NMOS transistors at each
memory bit location, as illustrated by the OR memory stage in Fig. 7.3.
Each transistor in Fig. 7.3 has two gates, a connected outer gate and an inner floating
(unconnected) gate that is surrounded by a highly insulating material. Programming occurs
when a high positive voltage is applied to the connected gate inducing a negative charge on
the floating gate which remains after the high voltage is removed. Then, when a decoder
line becomes active (HV), the negative charge prevents the NMOS from being turned ON,
thereby maintaining a 1(H) at the memory bit position. This is equivalent to blowing a
fusible link in Fig. 7.2. If all floating-gate NMOS in an OR column are so programmed,
the output from the inverter is 0(H). But if a decoder line is active to any unprogrammed
floating-gate NMOS, that bit position will be pulled to ground 0(H), causing the output to
be 1(H) from the inverter — again, the OR function.
Erasure of a programmed floating-gate NMOS occurs by removing the negative charge
on its floating gate. This charge can remain on the gate nearly indefinitely, but if the floating
gate in a UVEPROM is exposed (through a "window") to ultraviolet light of a certain
frequency, the negative charge on the floating gate is removed and erasure occurs. Similarly,
if a voltage of negative potential is applied to the outer connected gate of an EEPROM,
removal of the negative charge occurs. The technology for the UVEPROMs and EEPROMs
differ somewhat as to the manner in which the floating gate is insulated; otherwise, they
share much in common.
Technologies other than those just described are used to manufacture PROMs. For ex-
ample, in bipolar PROMs, diodes with fusible links replace the NMOS in Fig. 7.2 with each
diode conducting in the A -> B direction (see blowup of the fusible link). Now, however,