Page 324 - Engineering Digital Design

CHAPTER 7

Programmable Logic

Devices

7.1 INTRODUCTION

A class of devices called programmable logic devices (or PLDs) can be thought of as
universal logic implementers in the sense that they can be configured (actually programmed)
by the user to perform a variety of specific logic functions. So useful and versatile are these
PLDs that one might question why any other means of design would ever be considered.
Well, the answer is, of course, that there is a time and place for a variety of approaches to
design — that is, no one single approach to design satisfies all possible problem situations.
However, the option to use PLDs offers the logic designer a wide range of versatile devices
that are commercially available for design purposes.
Some PLDs are made to perform only combinational logic functions; others can per-
form both combinational and sequential logic functions. This chapter will consider those
PLDs capable of performing both combinational and sequential logic functions, but the
exemplar applications will be limited to combinational logic design. Four commonly used
PLDs considered here are the read-only memory (ROM) devices and their subgroups, the
field programmable logic array (FPLA) devices, the programmable array logic (PAL) de-
vices and their subgroups, and field programmable gate arrays (FPGAs) and subgroups.
Other PLDs include erasable programmable logic devices (EPLDs), including erasable
programmable ROMs, generic array logic (GAL) devices, and field programmable logic
sequencers (FPLSs). Except for FPGAs, most of the PLDs mentioned have some com-
monality, namely a two-level AND/OR configuration. What is connected to the AND/OR
network distinguishes one PLD from another. The development that follows attempts to
illustrate the differences between these various PLDs and to provide a few useful examples
of their application to combinational logic design.

7.2 READ-ONLY MEMORIES

A ROM is an n-input/m-output device composed of a nonprogrammable decoder (ANDing)
stage and a programmable (OR) stage as illustrated in Fig. 7.1. Bit combinations of the n

295