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7.3 PROGRAMMABLE LOGIC ARRAYS 301

section would be required. Recall that the three-level logic circuit for the cascadable 2-bit
comparator in Fig. 6.28 has a gate/input tally of only 23/67.

7.3 PROGRAMMABLE LOGIC ARRAYS

Like the ROM, the PLA is an n-input/ra-output device composed of an input ANDing stage
and a memory (ORing) output stage. Unlike the ROM, however, both stages of the PLA
are programmable, as indicated by the block diagram in Fig. 7.5. The AND matrix (array)
generates the product terms (p-terms), while the OR matrix ORs the appropriate product
terms together to produce the required SOP functions.
The dimensions of a PLA are specified by using three numbers:

n x p x m
t t t
No. of No. of No. of
inputs product outputs
terms

The number p gives the maximum number of product terms (p-terms) permitted by the
PLA. The magnitude of p is set by the PLA manufacturer based on expected user needs
and is usually much less than 2", the decoder output of a ROM. For example, a PLA
specified by dimensions 16 x 48 x 8 would have 16 possible inputs and could gener-
ate 8 different outputs (representing 8 different SOP expressions) composed of up to 48
unique ORed p-terms. A p-term may or may not be a minterm. In contrast, a 16-input
16
ROM could generate the specified number of outputs with up to 2 = 65,536 minterms.

p product term (P-term) lines

1 |r
F
—> o. x
-> n-lnput -^ OR Memory
n Inputs < AND Array • Array . > m Outputs
(programmable) • (programmable) •
P
— > o .
m

n x p x m PLA
FIGURE 7.5
Block diagram for an n-input/m -output PLA showing the programmable AND and OR array stages
and the p product-term lines.