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302 CHAPTER 7 / PROGRAMMABLE LOGIC DEVICES

The comparison here is 48 p-terms and 48 ORing connections for the unprogrammed PLA
vs 65,536 minterms and 65,536 ORing connections for the unprogrammed ROM, a vast
difference in hardware. Typically, commercial PLAs have inputs ranging in number from
8 to 16, with 20 to 60 addressable p-terms and up to 10 outputs that may or may not
have controlled polarity by using XOR gates on the output lines (see Subsection 3.9.6).
PLA 1C chips of most any n x p x m dimensions can be manufactured to user specifi-
cations.
PLAs, like ROMs, are constructed of interconnecting arrays of switching elements that
perform the AND and OR operations. Members of the PLA family fall generally into two
classes:

• Programmable logic arrays (PLAs) — Mask programmable AND and OR stages
• Field programmable logic arrays (FPLAs) — One-time programmable AND
and OR stages

Thus, PLAs are programmed during fabrication in a manner similar to ROMs, while FPLAs
are write-once programmed by the user.
Shown in Fig. 7.6 is the MOS version for an unprogrammed n x p x m FPLA illustrating
the programmable bit connections in both the AND and OR array sections. A given p-term
row can become active, P/(//) = 1(#), iff all of the NMOS switches on the AND side are
either disconnected or turned OFF. If any one of the NMOS in a p-term row is turned ON,
then that row is pulled low, 0(H). An active p-term line causes a connected OR bit position
in its path to be pulled low, resulting in a 1(H) from the output tri-state inverter. The buffer
between the AND and OR stages is necessary to boost and sharpen the signal. Such a buffer
could consist of two CMOS inverters. Notice that tri-state drivers provide an active low
enable control on the OR stage.
The programming of a PLA is best understood by considering the 3-input/2-output FPLA
segment in Fig. 7.7. Here, the single p-term line is programmed to generate O\ (H) = !(//)
and Oo(H) = 0(//) any time the p-term I\ • IQ becomes active. Notice that both NMOS bit
positions for 7 2 are disconnected together with those for the I\(L) and /o(#) lines. Thus, if
/i is 0(H) and /o is 1(H), the p-term line Pj(H) is forced active which, in turn, causes output
O\(H) to become !(//), but not output Oo(H), whose bit position has been disconnected,
causing it to become 0(/f). In effect, disconnection (blowing) of a fusible link in the AND
plane actually "makes the connection" of the p-term input (// or 7 ;), and disconnection
of a fusible link in the OR plane stores a l(H) = 0(L). These facts may make it easier to
understand the symbolic representations illustrated in Subsection 7.3.1.

7.3.1 PLA Applications
Unlike the programming of ROMs which require canonical data, PLAs require minimum
or reduced SOP data. Thus, the most efficient application of an FPLA would be one for
which the needed product terms fit within the FPLA's limited p-term capability. A good
example is the FPLA implementation of the 4-bit combinational shifter of Fig. 6.37. Shown
in Fig. 7.8 is the truth table (reproduced from Fig. 6.37a) and the EV K-maps and minimum
cover for this shifter. The minimum output expressions for this shifter are obtained directly