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7.4 PROGRAMMABLE ARRAY LOGIC DEVICES 307

7.4 PROGRAMMABLE ARRAY LOGIC DEVICES

Perhaps the most widely used PLD is the programmable array logic (PAL) device. The
PAL device can be programmed only in the AND plane. For reference purposes the main
differences between ROMs, PLAs and PAL devices may be stated as follows:

ROM devices — Programmable in the OR plane only
PLA devices — Programmable in both AND and OR planes
PAL devices — Programmable in the AND plane only

Thus, a PLA device may be thought of as a combination of ROM and PAL device pro-
gramming characteristics. PAL devices, like PLAs, commonly include a variety of devices
external to their OR planes, including XOR gates, AND-OR-invert logic, and registered
outputs.
The acronym PAL is a registered trademark of Advanced Micro Devices, Inc. Therefore,
hereafter it will be understood that use of the name PAL will acknowledge AMD's right of
trademark for all devices that carry the name PAL.
PAL devices characteristically provide a fixed number of p-terms per output and cannot
take advantage of shared Pis. This is illustrated by the unprogrammed 8 x 20 x 4 PAL
device shown in Fig. 7.11, which allows up to five p-terms per output. If the number of
p-terms for a given output exceeds the number provided by the PAL device, the remaining
p-terms can be given to another column output line, and the two ORed external to the OR
plane. Thus, in the case of the 4-bit shifter, the Y Q(H) output, requiring six p-terms, would
have to have one or more of its p-terms given to a fifth output line (not shown) and the two
lines ORed external to the OR plane. The MOS version of a basic PAL device would look
like that for the PLA in Fig. 7.6, except that the NMOS bit positions in the OR stage would
be permanently connected — no fusible links.
The basic PAL device simply employs an AND and OR section either in the form of
AND/OR or AND/NOR as in Fig. 7.12a. However, the output logic of most PAL devices
goes beyond the basic PAL. Shown in Fig. 7.12b is a segment of a PAL device that supports
an L-type (logic-type) macrocell consisting of a controlled inverter (XOR gate), an AND-
controlled output enable, and a feedback path. The feedback path is useful for cascading
combinational logic functions, or for the design of asynchronous (self-timed) sequential
machines covered in Chapter 14. In either case, one output function is fed back to become
the input in the generation of another output function.
Macrocells containing on-chip flip-flops are also found in PAL devices, as illustrated in
Fig. 7.12c. These are called R-type (registered-type) macrocells; they support feedback from
a flip-flop output and a controlled tri-state driver/enable. Both the clock signal and the output
enable signal can be supplied externally or can be generated from within the PAL device.
PAL devices with R-type macrocells are useful in the design of synchronous (clock-driven)
sequential machines, which are discussed at length in Chapters 10 through 13. The descrip-
tion of flip-flops and the details of their design and operation are presented in Chapter 10.
The versatility of PAL devices is improved significantly by the use of V-type (variable-
type) macrocells such as that illustrated in Fig. 7.13. Now, the output signal generated from
a 4-to-l MUX can be combinational or registered depending on the data select inputs Si
and So whose logic values are set by programming fusible links. Thus, data select inputs