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Sign-bit carry
1
5 3 0011010 1 0011010 1
+7 5 0100101 1
+ 12 8 ,01000000 0

' Sign-bit overflow error

0 1
L Sign bit '—Sign bit

(a) (b)

FIGURE 8.10
Eight-bit additions showing sign bits and final two carries, (a) Sign-bit overflow error created for sum
exceeding decimal 127. (b) Correct sign bit for sum equal to 127.

C n., w s.
n n-1 B n-i(H)
0 0 1 0 1 I A/S(H)
J L
1 1 0 1 0
a 9- )
k B / \

B n.,(H)
A/S(H) C A

H
S E rrorDet( ) S^H)
(b)

(C)
FIGURE 8.11
Overflow error detection circuits for sign-bit stage, (a) Truth table for overflow error in the sign-
bit stage, (b) Overflow error detection circuit by using external data inputs and the sum output, (c)
Alternative overflow error detection circuit by using input and output carries.